A cache device and a method of using the same for data accesses according to the invention. Particularly, the cache device has a prefetch queue comparing circuit which comprises a cache hit/miss judging circuit, an address queue register and a prefetch condition judging circuit. The cache hit/miss judging circuit is used to judge whether a currently-read address coming from a bus is of cache hit or cache miss, wherein the address consists of an index address and a tag address. The address queue register directly stores the index address of the currently-read address plus a corresponding first one-bit flag signal if the cache hit/miss judging circuit judges that the currently-read address is of cache hit. The prefetch condition judging circuit is used to judge whether the index address of the currently-read address is the same as any index addresses already stored in the address queue register if the cache hit/miss judging circuit judges that the currently-read address is of cache miss. If the index address is not the same as any index address still stored in the address queue register, a corresponding tag address and data originally stored in a tag memory and a data memory, respectively are renewed in an asynchronous way.