公开(公告)号：US08478581B2

公开(公告)日：2013-07-02

申请号：US12692667

申请日：2010-01-25

Applicant: Chung-ching Chen

Inventor： Chung-ching Chen

IPC: G06F17/28

CPC classification number: G06F17/2872 ,  G06F17/274

Abstract: An embodiment provides (a) a method and system for representing natural languages in a common machine-readable form, including the thorough design of the lexicon and grammar, the resulting representation called interlingua, (b) a method and system for using a computer to convert a text of a natural language into and out of a coded text of said interlingua representation, including a programming framework which is independent of other languages, said system is called interlingua engine, and (c) a method and system of machine translation using said interlingua engine, said system called interlingua machine translation system. Alternative embodiments are described.

Abstract translation: 一个实施例提供（a）用于以通用机器可读形式表示自然语言的方法和系统，包括词汇和语法的彻底设计，所得到的表示为interlingua，（b）使用计算机的方法和系统 将自然语言的文本转换成所述国际语言表示的编码文本，包括独立于其他语言的编程框架，所述系统被称为语言间引擎，以及（c）使用所述语言的机器翻译的方法和系统 国际语言引擎，称系统称为国际语言机器翻译系统。 描述了替代实施例。

公开(公告)号：US08405678B2

公开(公告)日：2013-03-26

申请号：US12149346

申请日：2008-04-30

Applicant: Kun-Nan Cheng ,  Yuan-Chuan Hsu ,  Hung-Yi Lin ,  Chung-Ching Chen

Inventor： Kun-Nan Cheng ,  Yuan-Chuan Hsu ,  Hung-Yi Lin ,  Chung-Ching Chen

IPC: G09G5/00 ,  G09G5/36

CPC classification number: G09G5/395 ,  G06T1/60 ,  G09G5/14 ,  G09G2310/0229 ,  G09G2340/0407 ,  G09G2340/12

Abstract: A display controller for displaying multiple windows and associated memory access method are provided. The display controller receives a first video source and a second video source for displaying multiple windows, and includes a line buffer, a deinterlacer, a scaler, and a memory interface unit. The line buffer buffers pixel data of a non-overlapped area of a main image associated with the first video source, and pixel data of a sub image associated with the second video source. The deinterlacer is coupled to the line buffer for selectively deinterlacing data in the line buffer. The scaler is coupled to the deinterlacer for selectively scaling data outputted from the deinterlacer. The memory interface unit is coupled to the line buffer for accessing an external memory.

Abstract translation: 提供了一种用于显示多个窗口和相关联的存储器访问方法的显示控制器。 显示控制器接收用于显示多个窗口的第一视频源和第二视频源，并且包括行缓冲器，去隔行扫描器，缩放器和存储器接口单元。 行缓冲器缓冲与第一视频源相关联的主图像的非重叠区域的像素数据和与第二视频源相关联的子图像的像素数据。 去隔行扫描器耦合到行缓冲器，用于在行缓冲器中选择性地去隔行数据。 缩放器耦合到去隔行扫描器，用于选择性地缩放从去交错器输出的数据。 存储器接口单元耦合到行缓冲器以访问外部存储器。

公开(公告)号：US20110184718A1

公开(公告)日：2011-07-28

申请号：US12692667

申请日：2010-01-25

Applicant: Chung-ching CHEN

Inventor： Chung-ching CHEN

IPC: G06F17/28 ,  G06F17/27

CPC classification number: G06F17/2872 ,  G06F17/274

Abstract: An embodiment provides (a) a method and system for representing natural languages in a common machine-readable form, including the thorough design of the lexicon and grammar, the resulting representation called interlingua, (b) a method and system for using a computer to convert a text of a natural language into and out of a coded text of said interlingua representation, including a programming framework which is independent of other languages, said system is called interlingua engine, and (c) a method and system of machine translation using said interlingua engine, said system called interlingua machine translation system. Alternative embodiments are described.

Abstract translation: 一个实施例提供（a）用于以通用机器可读形式表示自然语言的方法和系统，包括词汇和语法的彻底设计，所得到的表示为interlingua，（b）使用计算机的方法和系统 将自然语言的文本转换成所述国际语言表示的编码文本，包括独立于其他语言的编程框架，所述系统被称为语言间引擎，以及（c）使用所述语言的机器翻译的方法和系统 国际语言引擎，称系统称为国际语言机器翻译系统。 描述了替代实施例。

公开(公告)号：US20110131354A1

公开(公告)日：2011-06-02

申请号：US12947966

申请日：2010-11-17

Applicant: Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

Inventor： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

IPC: G06F13/38

CPC classification number: G06F17/5068

Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Abstract translation: 通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。 定义模块根据多个I / O的引脚配置来定义映射表。 映射表包括多个IO和多个存储器功能之间的对应关系。 检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索对应于映射表的控制信息。 生成模块根据控制信息生成硬件描述语言（HDL）文件。 布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

公开(公告)号：US06321301B1

公开(公告)日：2001-11-20

申请号：US09372922

申请日：1999-08-12

Applicant: Ming-Fen Lin ,  Chung-Ching Chen ,  Ming-Tsan Kao

Inventor： Ming-Fen Lin ,  Chung-Ching Chen ,  Ming-Tsan Kao

IPC: G06F1208

CPC classification number: G06F12/0862

Abstract: A cache device and a method of using the same for data accesses according to the invention. Particularly, the cache device has a prefetch queue comparing circuit which comprises a cache hit/miss judging circuit, an address queue register and a prefetch condition judging circuit. The cache hit/miss judging circuit is used to judge whether a currently-read address coming from a bus is of cache hit or cache miss, wherein the address consists of an index address and a tag address. The address queue register directly stores the index address of the currently-read address plus a corresponding first one-bit flag signal if the cache hit/miss judging circuit judges that the currently-read address is of cache hit. The prefetch condition judging circuit is used to judge whether the index address of the currently-read address is the same as any index addresses already stored in the address queue register if the cache hit/miss judging circuit judges that the currently-read address is of cache miss. If the index address is not the same as any index address still stored in the address queue register, a corresponding tag address and data originally stored in a tag memory and a data memory, respectively are renewed in an asynchronous way.

Abstract translation: 根据本发明的缓存设备及其使用该数据访问的方法。 特别地，高速缓存设备具有包括高速缓存命中/未命中判断电路，地址队列寄存器和预取条件判断电路的预取队列比较电路。 高速缓存命中/未命中判断电路用于判断来自总线的当前读取地址是否为缓存命中或高速缓存未命中，其中该地址由索引地址和标签地址组成。 如果高速缓存命中/未命中判断电路判断当前读取的地址是缓存命中，地址队列寄存器直接存储当前读取地址的索引地址加相应的第一个1比特标志信号。 如果高速缓存命中/未命中判断电路判断当前读取的地址是否是，则预取条件判断电路用于判断当前读取地址的索引地址是否与已经存储在地址队列寄存器中的任何索引地址相同 缓存未命中 如果索引地址与仍然存储在地址队列寄存器中的任何索引地址不同，则分别以异步方式更新原始存储在标签存储器和数据存储器中的相应标签地址和数据。

公开(公告)号：US6073881A

公开(公告)日：2000-06-13

申请号：US135746

申请日：1998-08-18

Applicant: Chung-ching Chen

Inventor： Chung-ching Chen

IPC: B64C39/00 ,  B64C29/00

CPC classification number: B64C39/001 ,  B64C29/0066 ,  F02C9/24

Abstract: A lift apparatus using the method of blowing air over the upper surface of the apparatus to generate lift by virtue of the balance of outside pressures against the body of the apparatus. It does this by using the expansion characteristic of supersonic gas stream in a divergent space to create low pressure above the upper surface and to maintain the attachment of the stream to the surface. For power source, it uses the hybrid internal combustion engine of a co-pending invention in its jet operation mode to jet the air. And it solves the working substance supply problem by recycling.

Abstract translation: 一种提升装置，其使用在设备的上表面上吹送空气的方法，以通过抵抗装置的主体的外部压力的平衡来产生升力。 它通过使用超音速气流在发散空间中的膨胀特性来产生在上表面上方的低压并且保持流到表面的附着。 对于动力源，其喷射操作模式使用共同未决发明的混合内燃机来喷射空气。 并通过回收解决了工作物质供应问题。

公开(公告)号：US08850248B2

公开(公告)日：2014-09-30

申请号：US13190645

申请日：2011-07-26

Applicant: Ping-Cheng Hou ,  Cheng-Yu Lu ,  Chieh-Wen Shih ,  Jen-Shi Wu ,  Chung-Ching Chen

Inventor： Ping-Cheng Hou ,  Cheng-Yu Lu ,  Chieh-Wen Shih ,  Jen-Shi Wu ,  Chung-Ching Chen

IPC: G06F1/00 ,  G06F1/04 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3268 ,  Y02D10/126 ,  Y02D10/154

Abstract: A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.

Abstract translation: 用于访问数据存储设备的多核电子系统包括多个处理器，数据传输接口和速率调整模块。 处理器分别提供带宽要求，并通过共享数据传输接口与数据存储设备进行通信。 速率调整模块接收带宽要求，根据带宽要求确定数据传输接口的传输速率。

公开(公告)号：US08782332B2

公开(公告)日：2014-07-15

申请号：US13167889

申请日：2011-06-24

Applicant: Chung-Ching Chen ,  Hsian-Feng Liu ,  Yu-Lin Chen

Inventor： Chung-Ching Chen ,  Hsian-Feng Liu ,  Yu-Lin Chen

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F13/1673

Abstract: A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.

Abstract translation: 提供了包括判断模块，确定模块和传输模块的DRAM控制器。 判断模块判断第一命令和第三命令之间的地址内容差异。 确定模块根据地址内容差异来确定与至少一个第二命令相关联的多个缓冲地址内容。 传输模块然后顺序地向DRAM发送第一命令，至少一个第二命令和第三命令。

公开(公告)号：US08635569B2

公开(公告)日：2014-01-21

申请号：US12947966

申请日：2010-11-17

Applicant: Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

Inventor： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Abstract translation: 通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。 定义模块根据多个I / O的引脚配置来定义映射表。 映射表包括多个IO和多个存储器功能之间的对应关系。 检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索与映射表相对应的控制信息。 生成模块根据控制信息生成硬件描述语言（HDL）文件。 布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

公开(公告)号：US20080266305A1

公开(公告)日：2008-10-30

申请号：US12149346

申请日：2008-04-30

Applicant: Kun-Nan Cheng ,  Yuan-Chuan Hsu ,  Hung-Yi Lin ,  Chung-Ching Chen

Inventor： Kun-Nan Cheng ,  Yuan-Chuan Hsu ,  Hung-Yi Lin ,  Chung-Ching Chen

IPC: G09G5/36 ,  G06T1/60

CPC classification number: G09G5/395 ,  G06T1/60 ,  G09G5/14 ,  G09G2310/0229 ,  G09G2340/0407 ,  G09G2340/12

Abstract: A display controller for displaying multiple windows and associated memory access method are provided. The display controller receives a first video source and a second video source for displaying multiple windows, and includes a line buffer, a deinterlacer, a scaler, and a memory interface unit. The line buffer buffers pixel data of a non-overlapped area of a main image associated with the first video source, and pixel data of a sub image associated with the second video source. The deinterlacer is coupled to the line buffer for selectively deinterlacing data in the line buffer. The scaler is coupled to the deinterlacer for selectively scaling data outputted from the deinterlacer. The memory interface unit is coupled to the line buffer for accessing an external memory.

Abstract translation: 提供了一种用于显示多个窗口和相关联的存储器访问方法的显示控制器。 显示控制器接收用于显示多个窗口的第一视频源和第二视频源，并且包括行缓冲器，去隔行扫描器，缩放器和存储器接口单元。 行缓冲器缓冲与第一视频源相关联的主图像的非重叠区域的像素数据和与第二视频源相关联的子图像的像素数据。 去隔行扫描器耦合到行缓冲器，用于在行缓冲器中选择性地去隔行数据。 缩放器耦合到去隔行扫描器，用于选择性地缩放从去交错器输出的数据。 存储器接口单元耦合到行缓冲器以访问外部存储器。