公开(公告)号：US5946005A

公开(公告)日：1999-08-31

申请号：US920139

申请日：1997-08-27

Applicant: Ming-Mao Chiang ,  Ruen-Rone Lee ,  Ming-Fen Lin

Inventor： Ming-Mao Chiang ,  Ruen-Rone Lee ,  Ming-Fen Lin

IPC: G06T15/00 ,  G09G5/36

CPC classification number: G06T15/005

Abstract: Disclosed is an improved computer graphics memory architecture. The architecture includes an address translation table (ATT) and a buffer. The address translation table receives information about desired pixel data and determines the physical address of the desired data. The buffer is connected to the ATT and has a dual bank which stores the color value and the Z value of a 3-D pixel. A buffer addressing method is also provided in which the address of the desired pixel information and associated control circuits may be quickly determined through an appropriate data arrangement in the buffer and an address transfer table.

Abstract translation: 公开了一种改进的计算机图形存储器架构。 该架构包括地址转换表（ATT）和缓冲区。 地址转换表接收关于期望像素数据的信息，并确定所需数据的物理地址。 缓冲器连接到ATT，并具有存储3-D像素的颜色值和Z值的双存储体。 还提供了缓冲器寻址方法，其中可以通过缓冲器中的适当数据布置和地址传送表来快速确定期望像素信息和相关控制电路的地址。

公开(公告)号：US06263410B1

公开(公告)日：2001-07-17

申请号：US09153679

申请日：1998-09-15

Applicant: Ming-Tsan Kao ,  Ming-Mao Chiang ,  Ming-Fen Lin ,  Won-Yih Lin

Inventor： Ming-Tsan Kao ,  Ming-Mao Chiang ,  Ming-Fen Lin ,  Won-Yih Lin

IPC: G06F1200

CPC classification number: G06F5/14 ,  G06F2205/102 ,  G06F2205/126

Abstract: An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f2

Abstract translation: 提供了一种用于控制异步双端口FIFO存储器的装置和方法。 异步FIFO可以在满足0.5f2

公开(公告)号：US06693632B2

公开(公告)日：2004-02-17

申请号：US09965184

申请日：2001-09-28

Applicant: Chieh-Chih Chang ,  Ming-Fen Lin ,  Chien-Lin Lien

Inventor： Chieh-Chih Chang ,  Ming-Fen Lin ,  Chien-Lin Lien

IPC: G06T1500

CPC classification number: G06T17/00

Abstract: A method of area partition in virtual environment is disclosed. It can be used to divide 3D (Three Dimensions) virtual environment into several subareas. The invention interposes neighboring subareas so that the subareas in the same plane and the subareas in adjacent planes mix with one another. Both the number of subareas adjacent to each subarea and the number of subareas an object crosses can be decreased, thus lowering the load in operations.

Abstract translation: 公开了一种虚拟环境中的区域划分方法。 它可用于将3D（三维）虚拟环境划分为多个子区域。 本发明插入相邻子区域，使得相同平面中的子区域和相邻平面中的子区域彼此混合。 每个子区域相邻的子区域的数量和对象交叉的子区域的数量都可以减少，从而降低了操作中的负载。

公开(公告)号：US06321301B1

公开(公告)日：2001-11-20

申请号：US09372922

申请日：1999-08-12

Applicant: Ming-Fen Lin ,  Chung-Ching Chen ,  Ming-Tsan Kao

Inventor： Ming-Fen Lin ,  Chung-Ching Chen ,  Ming-Tsan Kao

IPC: G06F1208

CPC classification number: G06F12/0862

Abstract: A cache device and a method of using the same for data accesses according to the invention. Particularly, the cache device has a prefetch queue comparing circuit which comprises a cache hit/miss judging circuit, an address queue register and a prefetch condition judging circuit. The cache hit/miss judging circuit is used to judge whether a currently-read address coming from a bus is of cache hit or cache miss, wherein the address consists of an index address and a tag address. The address queue register directly stores the index address of the currently-read address plus a corresponding first one-bit flag signal if the cache hit/miss judging circuit judges that the currently-read address is of cache hit. The prefetch condition judging circuit is used to judge whether the index address of the currently-read address is the same as any index addresses already stored in the address queue register if the cache hit/miss judging circuit judges that the currently-read address is of cache miss. If the index address is not the same as any index address still stored in the address queue register, a corresponding tag address and data originally stored in a tag memory and a data memory, respectively are renewed in an asynchronous way.

Abstract translation: 根据本发明的缓存设备及其使用该数据访问的方法。 特别地，高速缓存设备具有包括高速缓存命中/未命中判断电路，地址队列寄存器和预取条件判断电路的预取队列比较电路。 高速缓存命中/未命中判断电路用于判断来自总线的当前读取地址是否为缓存命中或高速缓存未命中，其中该地址由索引地址和标签地址组成。 如果高速缓存命中/未命中判断电路判断当前读取的地址是缓存命中，地址队列寄存器直接存储当前读取地址的索引地址加相应的第一个1比特标志信号。 如果高速缓存命中/未命中判断电路判断当前读取的地址是否是，则预取条件判断电路用于判断当前读取地址的索引地址是否与已经存储在地址队列寄存器中的任何索引地址相同 缓存未命中 如果索引地址与仍然存储在地址队列寄存器中的任何索引地址不同，则分别以异步方式更新原始存储在标签存储器和数据存储器中的相应标签地址和数据。

公开(公告)号：US06373495B1

公开(公告)日：2002-04-16

申请号：US09333567

申请日：1999-06-21

Applicant: Ming-Fen Lin ,  Tung-Chieh Tsai ,  Hsiang-Chi Lin

Inventor： Ming-Fen Lin ,  Tung-Chieh Tsai ,  Hsiang-Chi Lin

IPC: G06T1140

CPC classification number: G06T15/04

Abstract: Texture mapping of a primitive object uses multiple levels of detail. The primitive object is a triangle having three vertices. The pixel coordinates of the three vertices and their corresponding texture mapped coordinates satisfy three linear equations derived from the equation representing the plane on which the triangle belongs to. An equivalent formula derived from a standard formula for the multiple levels of detail can be computed by a plurality of constants forming the three linear equations. The plurality of constants are first determined by using the pixel coordinates and the corresponding texture mapped coordinates of the three vertices. By substituting the constants into the equivalent formula, the value for the multiple levels of detail can be computed. A lookup table is used to determine log2 function values that are required in the equivalent formula. The method can be realized by simple hardware and a high precision log2 lookup table to accomplish high quality texture mapping.

Abstract translation: 原始对象的纹理映射使用多个细节级别。 原始对象是具有三个顶点的三角形。 三个顶点的像素坐标及其对应的纹理映射坐标满足从表示三角形所属平面的方程导出的三个线性方程。 可以通过形成三个线性方程的多个常数来计算从多个细节级别的标准公式导出的等效公式。 首先通过使用三个顶点的像素坐标和对应的纹理映射坐标来确定多个常数。 通过将常数代入等价公式，可以计算多级细节的值。 查找表用于确定等效公式中所需的log2函数值。 该方法可以通过简单的硬件和高精度的log2查找表来实现，从而实现高质量的纹理映射。

公开(公告)号：US06751599B2

公开(公告)日：2004-06-15

申请号：US09741612

申请日：2000-12-19

Applicant: Chin-Chen Chang ,  Shu-Kai Yang ,  Ding-Zhou Duan ,  Ming-Fen Lin

Inventor： Chin-Chen Chang ,  Shu-Kai Yang ,  Ding-Zhou Duan ,  Ming-Fen Lin

IPC: G06F1518

CPC classification number: G06N7/02

Abstract: A method of operating a fuzzy inference system to simplify a mesh capable of producing a high-quality approximate mesh and retaining good characteristics and appearance so that a good visual effect emerges. The invention utilizes a fuzzy inference system to integrate mesh attributes and estimate the cost in removing certain data, which serve as a criteria for mesh simplification. Hence, the invention is suitable for progressive meshes, multiresolution modeling rendering and progressive transmission on a network.

Abstract translation: 一种操作模糊推理系统的方法，以简化能够产生高质量近似网格并保持良好特征和外观的网格，从而出现良好的视觉效果。 本发明利用模糊推理系统对网格属性进行整合，并估算去除特定数据的成本，作为网格简化的标准。 因此，本发明适用于网络上的渐进网格，多分辨率建模呈现和逐行传输。