- 专利标题: Voltage level converter circuit improved in operation reliability
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申请号: US09515594申请日: 2000-02-29
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公开(公告)号: US06344766B1公开(公告)日: 2002-02-05
- 发明人: Masaaki Mihara , Yasuhiko Taito
- 申请人: Masaaki Mihara , Yasuhiko Taito
- 优先权: JP9-251860 19970917
- 主分类号: H03K190185
- IPC分类号: H03K190185
摘要:
A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
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