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公开(公告)号：US06344766B1
公开(公告)日：2002-02-05
申请号：US09515594
申请日：2000-02-29
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
IPC分类号： H03K190185
摘要： A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
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公开(公告)号：US6049243A
公开(公告)日：2000-04-11
申请号：US45568
申请日：1998-03-23
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
摘要： A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
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3.发明授权Semiconductor integrated circuit device with adjustable high voltage detection circuit 失效具有可调高压检测电路的半导体集成电路器件
公开(公告)号：US6008674A
公开(公告)日：1999-12-28
申请号：US927796
申请日：1997-09-11
摘要： A semiconductor integrated circuit device with a high voltage detection circuit comprises a high voltage step-down circuit for stepping down a high voltage input and outputting the stepped-down voltage, a reference voltage generator for generating plural reference voltages, a reference voltage selector for selecting one of the plural reference voltages, a high voltage detection circuit for comparing the stepped down voltage with the selected reference voltage to detect a high voltage and a control circuit for controlling the voltage drop of the high voltage and selection of the plural reference voltages to set the high voltage to be detected by the high voltage detector. There is also disclosed semiconductor integrated circuit having a high voltage step-down circuit for outputting plural stepped-down voltages having a fine tuner for fine-tuning each of the plural stepped-down voltages wherein a stepped-down voltage having been tuned finely is compared with a reference voltage given by a reference voltage generator.
摘要翻译： 具有高电压检测电路的半导体集成电路装置包括用于降压高压输入并输出降压的高压降压电路，用于产生多个参考电压的参考电压发生器，用于选择的参考电压选择器 多个参考电压中的一个，用于将降压电压与所选择的参考电压进行比较以检测高电压的高电压检测电路，以及用于控制高电压的电压降和选择多个参考电压的控制电路以设置 由高电压检测器检测的高电压。 还公开了一种具有高压降压电路的半导体集成电路，用于输出具有微调整器的多个降压电压，用于微调多个降压电压中的每一个，其中比较精调的降压电压 具有由参考电压发生器给出的参考电压。
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公开(公告)号：US06198331B1
公开(公告)日：2001-03-06
申请号：US09516212
申请日：2000-02-29
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
IPC分类号： H03K190185
摘要： A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
摘要翻译： 电压电平转换器电路包括第一节点，具有根据输入电压的电压的第二节点，连接在第二节点和第一节点之间的P沟道MOS晶体管，当输入电压达到L电平时导通;第三节点 连接在第三节点和第四节点之间的第一N沟道MOS晶体管，当所述输入电压达到H电平时导通;第二N沟道MOS晶体管，连接在所述第一节点和所述第四节点之间， 并且具有提供减轻信号的栅极，第三N沟道MOS晶体管和用于根据第一电压的电平提供缓解信号的电平确定电路。
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5.发明授权
公开(公告)号：US5872476A
公开(公告)日：1999-02-16
申请号：US716846
申请日：1996-09-10
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
IPC分类号： G11C17/00 , G11C16/06 , H03K3/356 , H03K17/10 , H03K19/0185 , H03L5/00 , H03K19/0175
CPC分类号： H03K3/356113
摘要： A level converter circuit includes a first CVSL (Cascade Voltage Switch Logic) circuit responsive to a voltage switching signal for providing a power supply voltage or an input voltage, and a second CVSL circuit responsive to a voltage equal to the power supply voltage or input voltage output from the first CVSL circuit for providing a positive input voltage or a negative input voltage. The level converter circuit can supply high positive and negative voltages required for a flash memory.
摘要翻译： 电平转换器电路包括响应于用于提供电源电压或输入电压的电压切换信号的第一CVSL（级联电压开关逻辑）电路和响应于等于电源电压或输入电压的电压的第二CVSL电路 从第一CVSL电路输出，以提供正输入电压或负输入电压。 电平转换器电路可以提供闪存所需的高正负电压。
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公开(公告)号：US08017994B2
公开(公告)日：2011-09-13
申请号：US12499220
申请日：2009-07-08
IPC分类号： H01L29/792
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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公开(公告)号：US20090310409A1
公开(公告)日：2009-12-17
申请号：US12499220
申请日：2009-07-08
IPC分类号： G11C16/04 , H01L29/792 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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公开(公告)号：US20070230251A1
公开(公告)日：2007-10-04
申请号：US11550335
申请日：2006-10-17
IPC分类号： G11C16/10
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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9.发明授权Boosting circuit configured with plurality of boosting circuit units in series 失效升压电路配置有多个串联的升压电路单元公开(公告)号：US06838928B2
公开(公告)日：2005-01-04
申请号：US10339327
申请日：2003-01-10
申请人： Masaaki Mihara
发明人： Masaaki Mihara
CPC分类号： H02M3/073
摘要： By supplying a clock signal from an OSC to four stages of boosting circuit units connected in series, the boosting circuit units are rendered active. A delay element is inserted in the line of the clock signal to prevent all the boosting circuit units from being rendered active at the same time by one clock signal. Since the boosting circuit unit is rendered active one by one by the provision of the delay element, current congregation from the power supply potential at the circuit element connected closest to the input terminal of the boosting circuit unit of the first stage can be prevented. Thus, a boosting circuit of a high boosting efficiency is achieved.
摘要翻译： 通过将来自OSC的时钟信号提供给串联连接的升压电路单元的四级，升压电路单元被激活。 延迟元件插入时钟信号的行中，以防止所有升压电路单元同时被一个时钟信号激活。 由于通过提供延迟元件使升压电路单元一个接一个地被激活，所以可以防止从最靠近第一级的升压电路单元的输入端子连接的电路元件处的电源电位的会聚。 因此，实现了高增压效率的升压电路。
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公开(公告)号：US06643207B2
公开(公告)日：2003-11-04
申请号：US10176633
申请日：2002-06-24
申请人： Masaaki Mihara
发明人： Masaaki Mihara
IPC分类号： G11C700
摘要： In a high-voltage detection circuit (10) for detecting a high voltage (VP) output from a high-voltage generation circuit (14), an output of the high-voltage generation circuit is dropped in voltage by a high-voltage drop circuit (13) to output a dropped voltage (VO), a reference-voltage generation circuit (11) generates a reference voltage (Vref) of a comparatively-high potential using the the high voltage (VP) as its power source, and a comparison circuit (12) compares the dropped voltage (VO) with the reference voltage (Vref) to control a high-voltage level.
摘要翻译： 在用于检测从高电压发生电路（14）输出的高电压（VP）的高电压检测电路（10）中，高压发生电路的输出由高压降电路 （13）输出下降电压（VO），基准电压生成电路（11）使用高电压（VP）作为其电源，生成比较高的电位的基准电压（Vref），并且进行比较 电路（12）将掉电电压（VO）与参考电压（Vref）进行比较，以控制高电压电平。
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