发明授权
US06349380B1 Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
有权
使用32位微处理器中的4和8字节页表项进行线性地址扩展和映射到物理内存
- 专利标题： Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
- 专利标题（中）： 使用32位微处理器中的4和8字节页表项进行线性地址扩展和映射到物理内存
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申请号： US09267796申请日： 1999-03-12
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公开(公告)号： US06349380B1公开(公告)日： 2002-02-19
- 发明人: Shahrokh Shahidzadeh , Bryant E. Bigbee , David B. Papworth , Frank Binns , Robert P. Colwell
- 申请人： Shahrokh Shahidzadeh , Bryant E. Bigbee , David B. Papworth , Frank Binns , Robert P. Colwell
- 主分类号： G06F9355
- IPC分类号： G06F9355
摘要：
A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.
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