公开(公告)号：US06349380B1

公开(公告)日：2002-02-19

申请号：US09267796

申请日：1999-03-12

申请人： Shahrokh Shahidzadeh ,  Bryant E. Bigbee ,  David B. Papworth ,  Frank Binns ,  Robert P. Colwell

发明人： Shahrokh Shahidzadeh ,  Bryant E. Bigbee ,  David B. Papworth ,  Frank Binns ,  Robert P. Colwell

IPC分类号： G06F9355

CPC分类号： G06F9/342 ,  G06F12/0292

摘要： A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

摘要翻译： 用于提供超过32位的扩展线性地址的微处理器。 可以通过将线性地址与段选择器扩展连接，或者通过连接来自两个寄存器的值来提供扩展线性地址。 执行线性地址到物理地址的分级转换，其中层级中的层数取决于线性地址是否是扩展线性地址。

公开(公告)号：US06289431B1

公开(公告)日：2001-09-11

申请号：US09013414

申请日：1998-01-26

申请人： Bryant E. Bigbee ,  Lance E. Hacking ,  Shahrokh Shahidzadeh ,  Shreekant S. Thakkar

发明人： Bryant E. Bigbee ,  Lance E. Hacking ,  Shahrokh Shahidzadeh ,  Shreekant S. Thakkar

IPC分类号： G06F1202

CPC分类号： G06F12/1009

摘要： A method and apparatus for accessing pages in physical memory, where the physical memory is described. The present invention provides a paged memory system having multiple page sizes. Pages of a first size are accessed via a page directory entry and a corresponding page table entry. The page directory entry stores a base physical address for a corresponding page table and control bits indicating permissions. The page table entry stores a base physical address of the page in memory. In one embodiment, the page table entry inherits permissions from the page directory entry. Pages of a second size are accessed via a page directory entry that stores a base physical address of the page and control bits indicating permissions associated with the page. In another embodiment, entries to the page directory table and the page table are 4-bytes in size and provide paging for memory up to 1.1 Terabytes in size.

摘要翻译： 一种用于访问物理存储器中的页面的方法和装置，其中描述了物理存储器。 本发明提供了一种具有多页尺寸的分页存储系统。 通过页面目录条目和对应的页面表项访问第一个大小的页面。 页目录条目存储相应页表的基本物理地址和指示许可的控制位。 页表条目将页面的基本物理地址存储在存储器中。 在一个实施例中，页表条目从页目录条目继承权限。 通过存储页面的基本物理地址的页目录条目和指示与页面相关联的权限的控制位来访问第二大小的页面。 在另一个实施例中，到页目录表和页表的条目大小为4字节，并为大小为1.1TB的内存提供寻呼。

公开(公告)号：US5946713A

公开(公告)日：1999-08-31

申请号：US914578

申请日：1997-08-18

申请人： Lance E. Hacking ,  Bryant E. Bigbee ,  Shahrokh Shahidzadeh ,  Shreekant S. Thakkar

发明人： Lance E. Hacking ,  Bryant E. Bigbee ,  Shahrokh Shahidzadeh ,  Shreekant S. Thakkar

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0802

摘要： The present invention relates to a computer system in which linear memory attributes are specified. Physical memory attributes may also be specified in physical attribute registers. A memory attribute palette (MAP) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.

摘要翻译： 本发明涉及一种其中规定了线性存储器属性的计算机系统。 物理存储器属性也可以在物理属性寄存器中指定。 存储器属性调色板（MAP）接收索引信号并响应于索引信号选择线性存储器属性。 有效存储器属性选择器接收所选择的线性存储器属性信号，并且如果存在物理存储器属性信号，并且响应于此，选择有效存储器属性信号以呈现有效存储器属性。 在优选实施例中，线性存储器属性可以可编程地写入一个或多个寄存器，从而允许程序或OS灵活地选择存储器属性，包括当前未使用的存储器属性。 本发明允许程序将选择的存储器属性应用于存储器的特定部分，从而允许计算机系统提供更高的性能。

公开(公告)号：US06857066B2

公开(公告)日：2005-02-15

申请号：US09990899

申请日：2001-11-16

申请人： Bryant E. Bigbee ,  Shivnandan Kaushik ,  Frank Binns

发明人： Bryant E. Bigbee ,  Shivnandan Kaushik ,  Frank Binns

IPC分类号： G06F1/04 ,  G06F9/30

CPC分类号： G06F9/30003

摘要： A method and apparatus comprising setting a register to a value executing a processing instruction to interpret the value and the at least one register verifying that the interpretation of the processing instruction is valid to ensure the at least one register contains a valid at least one string scanning the string in the register for multiplier scanning the string in the register for a frequency and determining a maximum operating frequency with the multiplier and frequency.

摘要翻译： 一种方法和装置，包括将寄存器设置为执行处理指令的值以解释所述值，并且所述至少一个寄存器验证所述处理指令的解释是否有效以确保所述至少一个寄存器包含有效的至少一个字符串扫描 寄存器中的字符串用于乘法器扫描寄存器中的字符串频率，并用乘数和频率确定最大工作频率。

公开(公告)号：US20170177429A1

公开(公告)日：2017-06-22

申请号：US14977354

申请日：2015-12-21

申请人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

发明人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC分类号： G06F11/07 ,  G06F3/06

CPC分类号： G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US08607235B2

公开(公告)日：2013-12-10

申请号：US11027445

申请日：2004-12-30

申请人： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

发明人： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

IPC分类号： G06F9/46

CPC分类号： G06F9/4843

摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

摘要翻译： 方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。 对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的顺控程序上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。

公开(公告)号：US20130073835A1

公开(公告)日：2013-03-21

申请号：US13675910

申请日：2012-11-13

申请人： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik

发明人： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik

IPC分类号： G06F9/30

CPC分类号： G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

摘要翻译： 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20080133898A1

公开(公告)日：2008-06-05

申请号：US11230721

申请日：2005-09-19

申请人： Chris J. Newburn ,  Dion Rodgers ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Gautham N. Chinya ,  Xiang Zou ,  Hong Wang

发明人： Chris J. Newburn ,  Dion Rodgers ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Gautham N. Chinya ,  Xiang Zou ,  Hong Wang

IPC分类号： G06F9/30

CPC分类号： G06F9/461

摘要： A technique for managing context state information. At least one embodiment includes a plurality of save area segments to store a plurality of machine context state information. One embodiment includes at least one in-use bit vector to indicate status of the plurality of machine context information.

摘要翻译： 一种用于管理上下文状态信息的技术。 至少一个实施例包括多个保存区段以存储多个机器上下文状态信息。 一个实施例包括至少一个用于指示多个机器上下文信息的状态的使用中位向量。

公开(公告)号：US08566567B2

公开(公告)日：2013-10-22

申请号：US13529630

申请日：2012-06-21

申请人： Chris J. Newburn ,  Robert Knight ,  Robert Geva ,  Dion Rodgers ,  Xiang Zou ,  Hong Wang ,  Bryant E. Bigbee ,  Ittai Anati

发明人： Chris J. Newburn ,  Robert Knight ,  Robert Geva ,  Dion Rodgers ,  Xiang Zou ,  Hong Wang ,  Bryant E. Bigbee ,  Ittai Anati

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F9/542 ,  G06F11/348 ,  G06F11/3612 ,  G06F2201/86 ,  G06F2201/885

摘要： Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

公开(公告)号：US20130219154A1

公开(公告)日：2013-08-22

申请号：US13837923

申请日：2013-03-15

申请人： Don A. Van Dyke ,  Michael Mishaeli ,  Ittai Anati ,  Baiju V. Patel ,  Will Deutsch ,  Rajesh Shah ,  Gilbert Neiger ,  James B. Crossland ,  Chris J. Newburn ,  Bryant E. Bigbee ,  Muhammad Faisal Azeem ,  John L. Reid ,  Dion Rodgers

发明人： Don A. Van Dyke ,  Michael Mishaeli ,  Ittai Anati ,  Baiju V. Patel ,  Will Deutsch ,  Rajesh Shah ,  Gilbert Neiger ,  James B. Crossland ,  Chris J. Newburn ,  Bryant E. Bigbee ,  Muhammad Faisal Azeem ,  John L. Reid ,  Dion Rodgers

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/30003 ,  G06F9/30101 ,  G06F9/461

摘要： Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.