公开(公告)号：US06349380B1

公开(公告)日：2002-02-19

申请号：US09267796

申请日：1999-03-12

申请人： Shahrokh Shahidzadeh ,  Bryant E. Bigbee ,  David B. Papworth ,  Frank Binns ,  Robert P. Colwell

发明人： Shahrokh Shahidzadeh ,  Bryant E. Bigbee ,  David B. Papworth ,  Frank Binns ,  Robert P. Colwell

IPC分类号： G06F9355

CPC分类号： G06F9/342 ,  G06F12/0292

摘要： A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

摘要翻译： 用于提供超过32位的扩展线性地址的微处理器。 可以通过将线性地址与段选择器扩展连接，或者通过连接来自两个寄存器的值来提供扩展线性地址。 执行线性地址到物理地址的分级转换，其中层级中的层数取决于线性地址是否是扩展线性地址。

公开(公告)号：US5584037A

公开(公告)日：1996-12-10

申请号：US571377

申请日：1995-12-13

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度和推测执行的微处理器的应用。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

公开(公告)号：US5564111A

公开(公告)日：1996-10-08

申请号：US315833

申请日：1994-09-30

申请人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

发明人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

IPC分类号： G06F9/38 ,  G06F11/00 ,  G06F12/10 ,  G06F11/34

CPC分类号： G06F9/3865 ,  G06F11/0751 ,  G06F12/1027 ,  G06F9/3842 ,  G06F2212/684

摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.

摘要翻译： 描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。 在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。 所存储的信息包括指令的线性地址和识别指令年龄的信息。 除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。 在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。 在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。 然后，一个分支被带入微码。 微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。 系统被刷新，微代码仅对实际退出的故障指令执行。 因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。 本文描述了方法和装置实现。

公开(公告)号：US5471633A

公开(公告)日：1995-11-28

申请号：US205842

申请日：1994-03-01

申请人： Robert P. Colwell ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  David W. Clift

发明人： Robert P. Colwell ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  David W. Clift

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F7/00

CPC分类号： G06F9/3824 ,  G06F9/30112 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A register alias table unit (RAT) with an idiom recognition mechanism for overriding partial width conditions stalls is described. A partial width stall condition occurs during the RAT renaming process when a logical source register being renamed is larger than the corresponding physical source register pointed to by a renaming table. An idiom recognizer detects uops that zero their logical destination register and sets and clears zero bits in an iRAT array accordingly. The zero bits indicate which portions of an entry's physical source register are known to be zeros. A partial width stall override mechanism overrides a partial width stall condition when the zero bits for the physical source register causing the partial width stall indicate that the "missing" portion of the physical source register contains zeros. The performance of a microprocessor implementing such a RAT renaming mechanism with an idiom recognizer is improved because common partial width stalls are avoided.

摘要翻译： 描述了具有用于覆盖部分宽度条件失速的习惯识别机制的寄存器别名表单元（RAT）。 当重新命名的逻辑源寄存器大于重命名表指向的相应物理源寄存器时，在RAT重命名过程期间发生部分宽度失速状况。 成语识别器检测uops，使其逻辑目标寄存器为零，并相应地设置和清除iRAT阵列中的零位。 零位指示条目的物理源寄存器的哪些部分已知为零。 当导致部分宽度失速的物理源寄存器的零位指示物理源寄存器的“丢失”部分包含零时，部分宽度失速覆盖机制将覆盖部分宽度失速条件。 通过习惯识别器实现这种RAT重命名机构的微处理器的性能得到改善，因为避免了普通的部分宽度档位。

公开(公告)号：US5179680A

公开(公告)日：1993-01-12

申请号：US707917

申请日：1991-05-30

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3891 ,  G06F12/0844 ,  G06F12/0875 ,  G06F9/30025 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/321 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3885

摘要： A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

摘要翻译： 一种用于将压缩形式的指令字存储在存储介质上的方法和装置，所述指令字具有多个指令字段，与每个指令字相关联的特征，具有至少等于 指令字中的指令字段。 每个指令字段与掩码字的位相关联，因此使用掩码字，只有非零指令字段需要存储在存储器中。 指令压缩方法有利地用在高速缓存未命中引擎中，用于在发生高速缓存未命中之后重新填充指令高速缓存的部分。

公开(公告)号：US6101597A

公开(公告)日：2000-08-08

申请号：US176370

申请日：1993-12-30

申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3824 ,  G06F9/383

摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM). Before an instruction is executed and its result data written back, the storage location address of the result is provided to the CAM and associatively compared with the source operand addresses stored therein. A CAM match and its accompanying match bit indicate that the result of the instruction to be executed will provide a source operand to the dependent instruction waiting in the reservation station. Using a bypass mechanism, if the operand is computed after dispatch of the dependent instruction, then the source operand is provided directly from the execution unit computing the source operand to a source operand input of the execution unit executing the dependent instruction.

摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多个机制来实现。 用于确定源操作数的可用性以及因此用于发送到可用执行单元的依赖指令的准备的机制依赖于在操作数本身实际计算之前源操作数的可用性的预期确定 执行另一条指令。 指令的源操作数的存储地址存储在内容可寻址存储器（CAM）中。 在执行指令并且其结果数据被写回之前，将结果的存储位置地址提供给CAM并与存储在其中的源操作数地址相关联地进行比较。 CAM匹配及其伴随的匹配位指示要执行的指令的结果将为在保留站等待的从属指令提供源操作数。 使用旁路机制，如果在分派依赖指令之后计算操作数，则将操作数从执行单元直接提供到计算源操作数到执行依赖指令的执行单元的源操作数输入。

公开(公告)号：US5987600A

公开(公告)日：1999-11-16

申请号：US851140

申请日：1997-05-05

申请人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

发明人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3842 ,  G06F9/3863

摘要： A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

摘要翻译： 用于协调处理器中的异常的方法和电路。 处理器为每个指令生成结果数据值和异常数据值，其中异常数据值指定相应指令是否引起异常。 处理器以顺序程序顺序将结果数据值提交给处理器的架构状态，并且如果异常由异常数据值之一指示，则提取异常处理程序来处理异常。 如果在结果数据值提交到处理器的架构状态时检测到异步事件，处理器将获取异步事件处理程序来处理异步事件。

公开(公告)号：US5627985A

公开(公告)日：1997-05-06

申请号：US177244

申请日：1994-01-04

申请人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

发明人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

IPC分类号： G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.

摘要翻译： 一种推测执行乱序处理器，包括一个包含多个物理寄存器的重排序电路，该多个物理寄存器缓冲整数和浮点运算的推测执行结果，以及一个包含多个提交状态寄存器的实际寄存器电路，该寄存器电路缓冲任一整数的提交执行结果 或浮点运算，具体取决于寄存器。 重排序和实际寄存器电路读取输入微操作的推测和确定的源数据值，并通过公共数据路径将推测和承诺的源数据值传输到微操作调度电路。 退出逻辑电路通过将推测执行结果从重新排序电路传送到实际寄存器电路来将推测执行结果提交到架构状态。

公开(公告)号：US5604878A

公开(公告)日：1997-02-18

申请号：US513679

申请日：1995-08-01

申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3873 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.

摘要翻译： 执行可能参与回写冲突的功能单位的管道延长，以避免冲突。 提供逻辑电路用于比较两个并发执行的执行单元管线的深度，以确定冲突是否会发展。 当看来两个执行单元将尝试同时回写时，将指示具有较短流水线的执行单元向其流水线添加一个阶段，将其结果存储在一个时钟周期的延迟缓冲器中。 冲突解决后，延长给定功能单位管道的指示将被撤销。 多级执行单元被设计为用信号通知保留站来延迟各种指令的发送以避免执行单元之间的冲突。

公开(公告)号：US5826094A

公开(公告)日：1998-10-20

申请号：US676887

申请日：1996-07-08

申请人： Robert P. Colwell ,  David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton

发明人： Robert P. Colwell ,  David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3828 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A mechanism for indicating within a register alias table (RAT) that certain data has become architecturally visible so that the RAT contains the most recent location of the certain data. Upon receiving the indication that data associated with a particular register is architecturally visible, if a subsequent operation uses the particular register as a source, the data will be supplied from the architecturally visible buffer instead of from an internal buffer (not architecturally visible). The internal buffer is implemented by a reorder buffer (ROB) which contains information associated with instructions that have not yet retired. The architecturally visible buffer is a retirement register file (RRF) which contains information associated with retired instructions. When an instruction retires, the register alias table is searched for the retiring physical register and will indicate within the register alias table that the data associated with the retiring physical register is located within the RRF only if the register alias table has not already (or concurrently) reassigned a new physical register to the logical register associated with the retiring physical register. If the logical register associated with the retiring physical register as been reassigned by subsequent instructions, then no update of the register alias table is required. Also provided is an embodiment for providing the above features in a system wherein the register ordering of the buffers can be altered via register exchange operations.

摘要翻译： 用于在寄存器别名表（RAT）中指示某些数据已经变得架构可见以使得RAT包含特定数据的最新位置的机制。 在接收到与特定寄存器相关联的数据在架构上可见的指示时，如果后续操作使用特定寄存器作为源，则数据将从架构可见缓冲器而不是内部缓冲器（不是架构可见）提供。 内部缓冲器由重新排序缓冲器（ROB）实现，该缓冲器包含与尚未退役的指令相关联的信息。 架构可见的缓冲区是一个退休寄存器文件（RRF），其中包含与退休指令相关的信息。 当指令退出时，对退出的物理寄存器搜索寄存器别名表，并且在寄存器别名表中指示只有当寄存器别名表尚未（或同时）时，与退出物理寄存器相关联的数据位于RRF内 ）将新的物理寄存器重新分配给与退出的物理寄存器相关联的逻辑寄存器。 如果由后续指令重新分配与退役物理寄存器相关联的逻辑寄存器，则不需要更新寄存器别名表。 还提供了一种用于在系统中提供上述特征的实施例，其中缓冲器的寄存器排序可以经由寄存器交换操作来改变。