- 专利标题: Fabrication process of semiconductor package and semiconductor package
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申请号: US09487682申请日: 2000-01-19
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公开(公告)号: US06365432B1公开(公告)日: 2002-04-02
- 发明人: Naoki Fukutomi , Yoshiaki Tsubomatsu , Fumio Inoue , Toshio Yamazaki , Hirohito Ohhata , Shinsuke Hagiwara , Noriyuki Taguchi , Hiroshi Nomura
- 申请人: Naoki Fukutomi , Yoshiaki Tsubomatsu , Fumio Inoue , Toshio Yamazaki , Hirohito Ohhata , Shinsuke Hagiwara , Noriyuki Taguchi , Hiroshi Nomura
- 优先权: JP6-48760 19940318; JP6-273469 19941108; JP7-7683 19950120; JP7-56202 19950315
- 主分类号: H01L2144
- IPC分类号: H01L2144
摘要:
A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
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