公开(公告)号：US06746897B2

公开(公告)日：2004-06-08

申请号：US10008616

申请日：2001-10-23

申请人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Fumio Inoue ,  Toshio Yamazaki ,  Hirohito Ohhata ,  Shinsuke Hagiwara ,  Noriyuki Taguchi ,  Hiroshi Nomura

发明人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Fumio Inoue ,  Toshio Yamazaki ,  Hirohito Ohhata ,  Shinsuke Hagiwara ,  Noriyuki Taguchi ,  Hiroshi Nomura

IPC分类号： H01L2144

CPC分类号： H01L21/568 ,  H01L21/4803 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83102 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/203 ,  H01L2924/351 ,  H05K3/20 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/0002

摘要： A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

公开(公告)号：US06365432B1

公开(公告)日：2002-04-02

申请号：US09487682

申请日：2000-01-19

申请人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Fumio Inoue ,  Toshio Yamazaki ,  Hirohito Ohhata ,  Shinsuke Hagiwara ,  Noriyuki Taguchi ,  Hiroshi Nomura

发明人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Fumio Inoue ,  Toshio Yamazaki ,  Hirohito Ohhata ,  Shinsuke Hagiwara ,  Noriyuki Taguchi ,  Hiroshi Nomura

IPC分类号： H01L2144

CPC分类号： H01L21/568 ,  H01L21/4803 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83102 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/203 ,  H01L2924/351 ,  H05K3/20 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/0002

摘要： A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

公开(公告)号：US5976912A

公开(公告)日：1999-11-02

申请号：US716362

申请日：1996-09-18

申请人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Fumio Inoue ,  Toshio Yamazaki ,  Hirohito Ohhata ,  Shinsuke Hagiwara ,  Noriyuki Taguchi ,  Hiroshi Nomura

发明人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Fumio Inoue ,  Toshio Yamazaki ,  Hirohito Ohhata ,  Shinsuke Hagiwara ,  Noriyuki Taguchi ,  Hiroshi Nomura

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/58 ,  H01L21/68 ,  H01L23/31 ,  H01L23/498 ,  H05K3/20 ,  H01L23/28

CPC分类号： H01L21/568 ,  H01L21/4803 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83102 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/203 ,  H01L2924/351 ,  H05K3/20

摘要： A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

摘要翻译： PCT No.PCT / JP95 / 00492 Sec。 371日期1996年9月18日 102（e）1996年9月18日PCT PCT 1995年3月17日PCT公布。 公开号WO95 / 26047 日期1995年9月28日提供了半导体封装基板，可以满足半导体高集成化的趋势。 将镍层电镀在电镀铜箔上以形成布线图案。 将LSI芯片安装在铜箔上，通过引线接合连接LSI芯片和布线图案的端子，然后用半导体密封环氧树脂密封。 只有铜箔用碱蚀刻剂溶解掉才能暴露镍。 对于具有低铜溶力的镍剥离器，去除镍层以露出布线图案。 涂覆阻焊剂，并且以使连接端子部分露出的方式形成图案。 将焊球放置在布线图案的露出部分，然后熔合。 布线图案通过焊球与外部印刷电路板连接。

公开(公告)号：US07187072B2

公开(公告)日：2007-03-06

申请号：US10705706

申请日：2003-11-10

申请人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Fumio Inoue ,  Toshio Yamazaki ,  Hirohito Ohhata ,  Shinsuke Hagiwara ,  Noriyuki Taguchi ,  Hiroshi Nomura

发明人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Fumio Inoue ,  Toshio Yamazaki ,  Hirohito Ohhata ,  Shinsuke Hagiwara ,  Noriyuki Taguchi ,  Hiroshi Nomura

IPC分类号： H01L21/00

CPC分类号： H01L21/568 ,  H01L21/4803 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83102 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/203 ,  H01L2924/351 ,  H05K3/20 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/0002

摘要： A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

摘要翻译： 提供了半导体封装基板，可以满足向半导体集成度高的趋势。 将镍层电镀在电镀铜箔上以形成布线图案。 将LSI芯片安装在铜箔上，通过引线接合连接LSI芯片和布线图案的端子，然后用半导体密封环氧树脂密封。 只有铜箔用碱蚀刻剂溶解掉才能暴露镍。 对于具有低铜溶力的镍剥离器，去除镍层以露出布线图案。 涂覆阻焊剂，并且以使连接端子部分露出的方式形成图案。 将焊球放置在布线图案的露出部分，然后熔合。 布线图案通过焊球与外部印刷电路板连接。

公开(公告)号：US5504992A

公开(公告)日：1996-04-09

申请号：US268866

申请日：1994-06-30

申请人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Toshio Yamazaki ,  Masahiko Itabashi ,  Hirohito Ohhata

发明人： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Toshio Yamazaki ,  Masahiko Itabashi ,  Hirohito Ohhata

IPC分类号： H05K3/42 ,  H05K3/46 ,  H05K3/02

CPC分类号： H05K3/428 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K3/4652 ,  Y10T29/49156 ,  Y10T29/49165

摘要： The object of the present invention is to provide a wiring board fabrication process which is, not only so smooth on the surface that a fine wiring pattern can be formed thereon, but also suitable for mounting electronic parts having fine pitch terminals.The present invention is a fabrication process of a wiring board which comprises a wiring conductive line embedded in the surface of an insulating substrate so that the upper face of the conductive line and the surface of the substrate are flat, and a through-hole land which is a conductive portion projected from the surface of the substrate in a through-hole portion, which is characterized in removing the conductive portion projected from the surface of the substrate in the through-hole portion so as to have a flat surface on the surface of the substrate.

摘要翻译： 本发明的目的在于提供一种线路板制造工艺，不仅在表面上光滑地形成精细的布线图案，而且还适合于安装具有细间距端子的电子部件。 本发明是一种布线板的制造工艺，其包括布置在绝缘基板的表面上的布线导线，使得导线的上表面和基板的表面平坦，以及通孔焊盘， 是在通孔部中从基板的表面突出的导电部，其特征在于，除去从通孔部中的基板的表面突出的导电部，使其在表面上具有平坦的表面 底物。

公开(公告)号：US06236108B1

公开(公告)日：2001-05-22

申请号：US09541041

申请日：2000-03-31

申请人： Yoshiki Sota ,  Koji Miyata ,  Toshio Yamazaki ,  Fumio Inoue ,  Hidehiro Nakamura ,  Yoshiaki Tsubomatsu ,  Yasuhiko Awano ,  Shigeki Ichimura ,  Masami Yusa ,  Yorio Iwasaki

发明人： Yoshiki Sota ,  Koji Miyata ,  Toshio Yamazaki ,  Fumio Inoue ,  Hidehiro Nakamura ,  Yoshiaki Tsubomatsu ,  Yasuhiko Awano ,  Shigeki Ichimura ,  Masami Yusa ,  Yorio Iwasaki

IPC分类号： H01L23495

CPC分类号： H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.

摘要翻译： 本发明的半导体封装芯片支撑基板包括绝缘支撑基板，设置在基板上的布线和设置在布线上的绝缘膜。 布线各自具有i）连接到半导体芯片电极的内部连接，以及ii）半导体芯片安装区域。 在绝缘支撑基板的一部分上还设置有开口，其中每个布线形成在绝缘支撑基板上，绝缘支撑基板是设置有内部连接的外部连接的部分。 绝缘膜形成在安装有半导体芯片的部分，覆盖布线的半导体芯片安装区域。

公开(公告)号：US6064111A

公开(公告)日：2000-05-16

申请号：US903996

申请日：1997-07-31

申请人： Yoshiki Sota ,  Koji Miyata ,  Toshio Yamazaki ,  Fumio Inoue ,  Hidehiro Nakamura ,  Yoshiaki Tsubomatsu ,  Yasuhiko Awano ,  Shigeki Ichimura ,  Masami Yusa ,  Yorio Iwasaki

发明人： Yoshiki Sota ,  Koji Miyata ,  Toshio Yamazaki ,  Fumio Inoue ,  Hidehiro Nakamura ,  Yoshiaki Tsubomatsu ,  Yasuhiko Awano ,  Shigeki Ichimura ,  Masami Yusa ,  Yorio Iwasaki

IPC分类号： H01L23/02 ,  H01L23/498 ,  H01L23/495 ,  H01L21/44

CPC分类号： H01L23/4985 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181

摘要： A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting a substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.

摘要翻译： 本发明的半导体封装芯片支撑基板包括绝缘支撑基板，设置在基板上的布线和设置在布线上的绝缘膜。 布线各自具有i）连接到半导体芯片电极的内部连接，以及ii）半导体芯片安装区域。 在绝缘支撑基板上的绝缘性支撑基板上形成有各自的配线的绝缘物的绝缘体上设置开口部，绝缘性支撑基板是设置有内部连接部的外部连接部的部分。 绝缘膜形成在安装有半导体芯片的部分，覆盖布线的半导体芯片安装区域。

公开(公告)号：US06223429B1

公开(公告)日：2001-05-01

申请号：US08981509

申请日：1998-07-30

申请人： Aizou Kaneda ,  Masaaki Yasuda ,  Itsuo Watanabe ,  Tomohisa Ohta ,  Fumio Inoue ,  Yoshiaki Tsubomatsu ,  Toshio Yamazaki ,  Hiroto Ohata ,  Kenzo Takemura ,  Akira Nagai ,  Osamu Watanabe ,  Naoyuki Shiozawa ,  Kazuyoshi Kojima ,  Toshiaki Tanaka ,  Kazunori Yamamoto

发明人： Aizou Kaneda ,  Masaaki Yasuda ,  Itsuo Watanabe ,  Tomohisa Ohta ,  Fumio Inoue ,  Yoshiaki Tsubomatsu ,  Toshio Yamazaki ,  Hiroto Ohata ,  Kenzo Takemura ,  Akira Nagai ,  Osamu Watanabe ,  Naoyuki Shiozawa ,  Kazuyoshi Kojima ,  Toshiaki Tanaka ,  Kazunori Yamamoto

IPC分类号： H05K330

CPC分类号： H01L24/83 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49883 ,  H01L24/29 ,  H01L24/32 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29384 ,  H01L2224/29444 ,  H01L2224/29469 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83951 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/00014

摘要： To provide a highly reliable semiconductor device structure that enables cost reduction in the production of packages, inclusive of the cost for chips, and may cause less changes in connection resistance even under conditions of a long-term environmental resistance test. In a semiconductor device comprising a semiconductor chip face-down bonded to a wiring board, it has a structure wherein projecting metal portions are provided at the opposing wiring board terminals without forming bumps on bonding pads of the chip, the whole chip surface is bonded with an organic, anisotropic conductive adhesive material, and the whole or at least an edge of the back of the chip is covered with a sealing material.

摘要翻译： 为了提供高可靠性的半导体器件结构，其能够降低封装的生产成本，包括芯片的成本，并且即使在长期耐环境测试的条件下也可能导致连接电阻的变化较小。在包括 面向下接合到布线板的半导体芯片，其结构是在相对的布线板端子处设置突出的金属部分，而不在芯片的焊盘上形成凸块，整个芯片表面用有机的各向异性导电 粘合剂材料，并且芯片的背面的整个或至少一个边缘被密封材料覆盖。

公开(公告)号：US4830691A

公开(公告)日：1989-05-16

申请号：US32249

申请日：1987-03-31

申请人： Akinari Kida ,  Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Takuya Yasuoka

发明人： Akinari Kida ,  Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Takuya Yasuoka

IPC分类号： H01L23/12 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

CPC分类号： H05K3/467 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4682 ,  H05K2201/0317 ,  H05K2201/0352 ,  H05K2203/0152 ,  H05K2203/061 ,  H05K2203/1438 ,  H05K2203/1581 ,  H05K3/007 ,  H05K3/4076 ,  H05K3/427 ,  H05K3/429 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A wiring board comprising (A) a base substrate on which the necessary wiring pattern has already been formed, and (B) a multi-layer substrate bonded to the wiring pattern side of said base substrate (A) and comprising heat-resistant resin layers and thin-film wiring patterns formed by a thin film forming method under vacuum can mount LSI chips on the substrate and realize increased density of signal wiring.

摘要翻译： 一种布线板，包括：（A）其上已经形成有必要的布线图案的基底基板，和（B）结合到所述基底基板（A）的布线图案侧的多层基板，并且包括耐热树脂层 并且通过真空下的薄膜形成方法形成的薄膜布线图案可以将LSI芯片安装在基板上，并实现信号布线的增加的密度。

公开(公告)号：US5426850A

公开(公告)日：1995-06-27

申请号：US983342

申请日：1992-11-30

申请人： Naoki Fukutomi ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Kouichi Kaitou ,  Yasunobu Yoshidomi ,  Yoshihiro Takahashi

发明人： Naoki Fukutomi ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Kouichi Kaitou ,  Yasunobu Yoshidomi ,  Yoshihiro Takahashi

IPC分类号： H05K3/04 ,  H05K3/20 ,  H05K3/42 ,  H05K3/46 ,  H05K3/06

CPC分类号： H05K3/428 ,  H05K3/205 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K3/04 ,  H05K3/4652 ,  H05K3/4658 ,  Y10S29/016 ,  Y10T29/49156 ,  Y10T29/49158

摘要： A wiring board is fabricated through the following steps:(A) forming, on one side of an elongated carrier metal foil made of a first metal, a thin layer with a second metal whose etching conditions are different from those of the first metal;(B) forming, on a surface of the thin layer, a desired wiring pattern with a third metal whose etching conditions are different from those of the second metal;(C) superposing the carrier metal foil on an insulating substrate with the side of the wiring pattern being positioned inside, whereby the wiring pattern is embedded in the insulating substrate; and(D) etching off the carrier metal foil and the thin layer at desired parts thereof.

摘要翻译： 通过以下步骤制造布线板：（A）在由第一金属制成的细长载体金属箔的一侧上形成具有与第一金属的蚀刻条件不同的第二金属的薄层; （B）在所述薄层的表面上形成与蚀刻条件不同于所述第二金属的第三金属的期望布线图案; （C）将所述载体金属箔叠置在所述布线图案的一侧位于绝缘基板上，由此将所述布线图案嵌入所述绝缘基板中; 和（D）在其所需部分刻蚀载体金属箔和薄层。