发明授权
- 专利标题: Digital delay line
- 专利标题(中): 数字延时线
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申请号: US09666118申请日: 2000-09-20
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公开(公告)号: US06366150B1公开(公告)日: 2002-04-02
- 发明人: Kouichi Ishimi
- 申请人: Kouichi Ishimi
- 优先权: JP9-134188 19970523; JP10-11847 19980123
- 主分类号: H03H1126
- IPC分类号: H03H1126
摘要:
In a multiplying circuit for providing a pulsed output clock signal having a frequency that is a multiple of a pulsed input clock signal, a delay of a digital delay line is initialized by initializing a counter when an external reset signal is input and when the number of pulses of the output clock signal from the clock generator is smaller than a predetermined multiplier. The delay of the digital delay line is set to a minimum value immediately following the initialization and then increased gradually in order to output the desired output clock signal.