公开(公告)号：US06828839B2

公开(公告)日：2004-12-07

申请号：US09511772

申请日：2000-02-24

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： H03H1126

CPC分类号： H03K5/131 ,  H03K2005/00071

摘要： Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

摘要翻译： 公开了一种时钟周期检测电路，其中可以通过预先执行粗略的周期调整来扩大相位调整和倍频器电路等的工作范围。 具有稍微重叠的操作范围和不同操作中心的多个延迟感测电路相对于通过延迟感测电路的输入时钟信号并联连接。 使用识别时钟信号经过的延迟感测电路的信号和时钟信号未通过的延迟感测电路，在短时间内粗略地感测时钟周期。

公开(公告)号：US06784713B2

公开(公告)日：2004-08-31

申请号：US10353051

申请日：2003-01-29

申请人： Herbert Haller ,  Harald Schurz

发明人： Herbert Haller ,  Harald Schurz

IPC分类号： H03H1126

CPC分类号： G05B9/03

摘要： In order to ensure safe and reliable time-delayed signal outputting with a simple redundant structure of a circuit arrangement, a common actuating element acts on two timers with associated A/D converters. In this case, the time delay which is predetermined by the actuating element and is relevant for the outputting of the switching signal is determined by forming the difference between a total resistance, detected by measurement, and a first resistance element, detected by measurement. This is followed by a comparison of the difference, which reflects second resistance elements that is determined by computation, with a second resistance element which is determined by measurement. The switching signal is then output with a time delay when there is a match between the second resistance element determined by measurement and that determined by computation.

摘要翻译： 为了通过电路装置的简单冗余结构确保安全可靠的时间延迟信号输出，公共致动元件作用在具有相关联的A / D转换器的两个定时器上。 在这种情况下，通过由致动元件预先确定并与开关信号的输出相关的时间延迟通过形成通过测量检测的由测量检测到的总电阻与第一电阻元件之间的差来确定。 之后是将通过计算确定的第二电阻元件与通过测量确定的第二电阻元件的差异进行比较。 然后当由测量确定的第二电阻元件与通过计算确定的第二电阻元件之间存在匹配时，开关信号以时间延迟输出。

公开(公告)号：US06774694B1

公开(公告)日：2004-08-10

申请号：US10328637

申请日：2002-12-24

申请人： Kenneth J. Stern ,  Jeff W. Barrell ,  Paul S. Cheung ,  Thomas Alan Gaiser

发明人： Kenneth J. Stern ,  Jeff W. Barrell ,  Paul S. Cheung ,  Thomas Alan Gaiser

IPC分类号： H03H1126

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K5/1508 ,  H03L7/07

摘要： A timing vernier applies a pair of stable bias voltages to intermediate points of an impedance string to establish reliable and calibratable delay cell biases for a fine multiplexer. A coarse input multiplexer is switched to a new timing signal substantially immediately after passing a prior valid timing signal to maximize the time prior to each valid output that the waveform is independent of the prior delay pattern. Logic circuitry is provided for three different phase differential regimes between successive timing signals to ensure that invalid output signals separated by less than a clock period are not produced. Mask commands are inserted into a series of timing control commands to equalize the average rates of writing and reading out the timing control commands with the mask commands skipped at readout.

摘要翻译： 定时游标器将一对稳定的偏置电压施加到阻抗串的中间点，以为精细多路复用器建立可靠和可校准的延迟单元偏移。 粗略输入多路复用器在通过先前的有效定时信号之后基本上立即被切换到新的定时信号，以使每个有效输出之前的时间最大化波形独立于先前的延迟模式。 为连续定时信号之间的三个不同的相位差方案提供逻辑电路，以确保不产生分开不到时钟周期的无效输出信号。 掩码命令被插入到一系列定时控制命令中，以平均写入速率和读出定时控制命令，并在读出时跳过掩码命令。

公开(公告)号：US06771106B2

公开(公告)日：2004-08-03

申请号：US10124673

申请日：2002-04-17

申请人： Keith Krasnansky

发明人： Keith Krasnansky

IPC分类号： H03H1126

CPC分类号： H03K5/08 ,  H03K5/131

摘要： A programmable delay circuit (100) maximizes processor bandwidth to external peripherals by eliminating wait state addition as the only way for satisfying timing requirements. Circuit (100) includes a programmable delay chain (102) connected to a hysteresis circuit (150). A processor control signal is fed into the programmable delay chain (102) which includes at least one switch (104-116) and at least one resistive element (118-126) connected together. A first feedback circuit (128) connects the output of the programmable delay chain (102) to the input (IN2) of the first embodiment (100) to keep the falling edge of the control signal the same without any significant added delay. The hysteresis circuit (150) which provides a stable signal connects to an output driver (180) for driving the processor control signal.

摘要翻译： 可编程延迟电路（100）通过消除等待状态相加作为满足定时要求的唯一途径，使处理器带宽达到外部外设。 电路（100）包括连接到磁滞回线（150）的可编程延迟链（102）。 处理器控制信号被馈送到可编程延迟链（102），其包括连接在一起的至少一个开关（104-116）和至少一个电阻元件（118-126）。 第一反馈电路（128）将可编程延迟链（102）的输出连接到第一实施例（100）的输入（IN2），以保持控制信号的下降沿相同而没有任何显着的附加延迟。 提供稳定信号的滞后电路（150）连接到用于驱动处理器控制信号的输出驱动器（180）。

公开(公告)号：US06771103B2

公开(公告)日：2004-08-03

申请号：US10087758

申请日：2002-03-05

申请人： Takamoto Watanabe ,  Hirohumi Isomura

发明人： Takamoto Watanabe ,  Hirohumi Isomura

IPC分类号： H03H1126

CPC分类号： G01S17/32 ,  G01S7/4915 ,  G01S7/493

摘要： In a shift clock signal generating apparatus, a delay line includes a plurality of unit delay elements connected in cascade. A reference clock signal propagates in the delay line while being successively delayed by the unit delay elements. Switches have first ends connected with output terminals of the unit delay elements respectively, and second ends connected with a shift clock signal output path. When specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as a shift clock signal. The specified one among the switches is determined on the basis of data representing a phase difference of the shift clock signal from the reference clock signal. The specified switch is set in its on position.

摘要翻译： 在移位时钟信号发生装置中，延迟线包括级联连接的多个单位延迟元件。 参考时钟信号在延迟线中传播，同时被单位延迟元件连续延迟。 开关具有分别与单元延迟元件的输出端相连的第一端，第二端与移位时钟信号输出路径连接。 当开关中指定的一个处于其接通位置时，将基准时钟信号延迟指定时间间隔所产生的延迟时钟信号通过指定的开关传送到移位时钟信号输出路径作为移位时钟信号。 基于表示来自基准时钟信号的移位时钟信号的相位差的数据来确定开关中指定的开关。 指定的开关设置在其开启位置。

公开(公告)号：US06650160B2

公开(公告)日：2003-11-18

申请号：US10059372

申请日：2002-01-31

申请人： Toshio Tanahashi

发明人： Toshio Tanahashi

IPC分类号： H03H1126

CPC分类号： H03K5/131 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0812 ,  H03L7/089

摘要： A method (and structure) of generating a two step variable length delay, including passing an input clock signal through a plurality of serially-interconnected delay elements, each delay element having a delay time interval dtc, thereby generating a corresponding plurality delayed signals. A set of m (where m is an integer greater than 2) of the plurality of delayed signals is switably selected. The selected m delayed signals form a first to an mth coarse adjustment delay signals. An nth coarse adjustment delay signal leads an (n+1)th coarse adjustment delay signal in phase by a time interval dtc (n is an integer being 1 or more and (m−1) or less). From the first to mth coarse adjustment delay signals, 2m fine adjustment delay signals are generated, where a jth fine adjustment delay signal leads a (j+1)th fine adjustment delay signal in a phase by a time interval dtc′, where time interval dtc′ is finer than the time interval dtc. The generation is achieved by amplifying the first to mth coarse adjustment delay signals, by mixing, for each n, waveforms of the nth and the (n+1)th coarse adjustment delay signals, and mixing waveforms of the mth and the first coarse adjustment delay signals. One of the 2m fine adjustment delay signals is outputted to be a selected variable length delay output signal.

摘要翻译： 一种产生两步可变长度延迟的方法（和结构），包括使输入时钟信号通过多个串联互连的延迟元件，每个延迟元件具有延迟时间间隔dtc，由此产生相应的多个延迟信号。 切换地选择多个延迟信号的m（m大于2的整数）的集合。 选择的m个延迟信号形成第一到第m个粗调延迟信号。 第n个粗调延迟信号使第（n + 1）个粗调延迟信号相位相差一个时间间隔dtc（n为1以上且（m-1）以下的整数）。 从第一至第m粗调延迟信号，产生2m微调延迟信号，其中第j个微调延迟信号将第（j + 1）个微调延迟信号以相位乘以时间间隔dtc'，其中时间间隔 dtc'比时间间隔dtc更精细。 通过对第n个和第（n + 1）个粗调延迟信号的每个n个波形混合，并且混合第m个和第一个粗调整延迟信号的混合波形， 延迟信号。 2m微调延迟信号之一被输出为选择的可变长度延迟输出信号。

公开(公告)号：US06633189B1

公开(公告)日：2003-10-14

申请号：US10037247

申请日：2001-10-23

申请人： Julian C. Gradinariu ,  John J. Silver

发明人： Julian C. Gradinariu ,  John J. Silver

IPC分类号： H03H1126

CPC分类号： H03H11/265

摘要： A circuit for providing substantially a constant delay of an electrical signal that compensates for voltage, temperature and process variations includes an inverter. A delay cell has an output that is coupled to the inverter. The delay cell includes a charge transistor coupled to a capacitor. A control circuit has an output that is coupled to a gate of the charge transistor. The output has a voltage that is proportional to a trip voltage of the inverter. The delay cell also has a discharge transistor. The control circuit contains a second output that is coupled to a gate of the discharge transistor. The second output has a voltage that is also proportional to the trip voltage of the inverter.

摘要翻译： 用于提供电压，温度和工艺变化的电信号的实质上恒定延迟的电路包括逆变器。 延迟单元具有耦合到逆变器的输出。 延迟单元包括耦合到电容器的充电晶体管。 控制电路具有耦合到充电晶体管的栅极的输出。 输出电压与变频器的跳闸电压成比例。 延迟单元还具有放电晶体管。 控制电路包含耦合到放电晶体管的栅极的第二输出端。 第二个输出电压也与变频器的跳闸电压成比例。

公开(公告)号：US06624679B2

公开(公告)日：2003-09-23

申请号：US09773269

申请日：2001-01-31

申请人： Francesco Tomaiuolo ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

发明人： Francesco Tomaiuolo ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC分类号： H03H1126

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

摘要： A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.

公开(公告)号：US06570426B2

公开(公告)日：2003-05-27

申请号：US10079158

申请日：2002-02-20

申请人： Takao Nakashimo

发明人： Takao Nakashimo

IPC分类号： H03H1126

CPC分类号： H03K5/135 ,  H03K5/08 ,  H03K5/13 ,  H03K2005/00247

摘要： In a delay circuit, a voltage detecting circuit is additionally provided. This voltage detecting circuit detects such a condition that a voltage appeared at a measuring terminal of the delay circuit is shifted from a predetermined voltage range for a time duration longer than, or equal to a preset time duration. Even when the measuring terminal of the delay circuit is short-circuited to the power supply voltage, or the ground potential, this delay circuit firmly inverts the output signal level based on delay time set by an internal delay circuit.

公开(公告)号：US06559700B2

公开(公告)日：2003-05-06

申请号：US09986144

申请日：2001-11-07

申请人： Masashi Yonemaru

发明人： Masashi Yonemaru

IPC分类号： H03H1126

CPC分类号： H03K19/1737 ,  H01L2924/0002 ,  H03K19/0013 ,  H03K19/01721 ,  H01L2924/00

摘要： A semiconductor integrated circuit includes a plurality of logical elements connected in series or parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and a buffer circuit connected between a logical element group including at least two of the plurality of logical elements and another logical element group including at least two of the plurality of logical elements.