发明授权
- 专利标题: Soft error rate tolerant latch
- 专利标题(中): 软错误率容错锁存器
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申请号: US09430977申请日: 1999-11-01
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公开(公告)号: US06380781B1公开(公告)日: 2002-04-30
- 发明人: Tanay Karnik , Krishnamurthy Soumyanath , Shekhar Y. Borkar
- 申请人: Tanay Karnik , Krishnamurthy Soumyanath , Shekhar Y. Borkar
- 主分类号: H03K312
- IPC分类号: H03K312
摘要:
A latch having increased soft error rate tolerance includes cross-coupled inverters having transistors with varying sizes. Diffusion regions of transistors coupled to storage nodes are kept small to reduce the effect of charge accumulation resulting from particles bombarding the bulk of an integrated circuit die. Transistors having gates coupled to the storage nodes are increased in size to increase the capacitance on the storage nodes. The reduced size of diffusion regions and increased size of gates on storage nodes combine to reduce the effects of accumulated charge. Diffusion region area is further reduced by reducing the size of pass gates that load normal data and scan data. A large capacitor is coupled to a feedback node within the cross-coupled inverters to further reduce the effect of accumulated charge.
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