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54 条记录 (耗时 0.023 秒)

    Soft error rate tolerant latch
    1.
    发明授权
    Soft error rate tolerant latch 有权
    软错误率容错锁存器

    公开(公告)号：US06380781B1

    公开(公告)日：2002-04-30

    申请号：US09430977

    申请日：1999-11-01

    申请人： Tanay Karnik ,  Krishnamurthy Soumyanath ,  Shekhar Y. Borkar

    发明人： Tanay Karnik ,  Krishnamurthy Soumyanath ,  Shekhar Y. Borkar

    IPC分类号： H03K312

    CPC分类号： G01R31/318525 ,  G01R31/31816

    摘要： A latch having increased soft error rate tolerance includes cross-coupled inverters having transistors with varying sizes. Diffusion regions of transistors coupled to storage nodes are kept small to reduce the effect of charge accumulation resulting from particles bombarding the bulk of an integrated circuit die. Transistors having gates coupled to the storage nodes are increased in size to increase the capacitance on the storage nodes. The reduced size of diffusion regions and increased size of gates on storage nodes combine to reduce the effects of accumulated charge. Diffusion region area is further reduced by reducing the size of pass gates that load normal data and scan data. A large capacitor is coupled to a feedback node within the cross-coupled inverters to further reduce the effect of accumulated charge.

    摘要翻译： 具有增加的软错误率容限的锁存器包括具有不同尺寸的晶体管的交叉耦合反相器。 耦合到存储节点的晶体管的扩散区域保持较小，以减少由颗粒轰击集成电路管芯的体积而产生的电荷累积的影响。 具有耦合到存储节点的栅极的晶体管的尺寸增加以增加存储节点上的电容。 扩散区尺寸减小，存储节点栅极尺寸增大，减少了累积电荷的影响。 通过减小加载正常数据和扫描数据的通孔的大小进一步减小扩散区域面积。 大电容器耦合到交叉耦合的反相器内的反馈节点，以进一步降低累积电荷的影响。

    Differential circuits employing forward body bias
    2.
    发明授权
    Differential circuits employing forward body bias 失效
    采用正向偏置的差分电路

    公开(公告)号：US06218892B1

    公开(公告)日：2001-04-17

    申请号：US09256842

    申请日：1999-02-24

    申请人： Krishnamurthy Soumyanath ,  Ali Keshavarzi ,  Vivek K. De ,  Shekhar Y. Borkar

    发明人： Krishnamurthy Soumyanath ,  Ali Keshavarzi ,  Vivek K. De ,  Shekhar Y. Borkar

    IPC分类号： G05F110

    CPC分类号： H01L27/0928 ,  H01L29/1087 ,  H03K19/0948 ,  H03L7/0812 ,  H03L7/0995

    摘要： In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.

    摘要翻译： 在一些实施例中，本发明包括具有差分放大器和体偏置控制电路的电路。 差分放大器包括第一和第二FET晶体管的差分对，以响应于输入电压信号至少部分地控制输出电压信号，第一和第二FET晶体管被配置为匹配并具有主体。 体偏置控制电路向身体提供体偏置电压信号，以将第一和第二FET晶体管置于正向体偏置状态。 差分放大器和体偏置电路可用于读出放大器，比较器，压控振荡器，延迟锁定环路和锁相环路以及其他电路。

    System and Method for Controlling Resonance Frequency of Film Bulk Acoustic Resonator Devices
    5.
    发明申请
    System and Method for Controlling Resonance Frequency of Film Bulk Acoustic Resonator Devices 有权
    用于控制膜体积声谐振器器件的谐振频率的系统和方法

    公开(公告)号：US20090039981A1

    公开(公告)日：2009-02-12

    申请号：US11836538

    申请日：2007-08-09

    申请人： Hiroyuki Ito ,  Hasnain Lakdawala ,  Ashoke Ravi ,  Krishnamurthy Soumyanath

    发明人： Hiroyuki Ito ,  Hasnain Lakdawala ,  Ashoke Ravi ,  Krishnamurthy Soumyanath

    IPC分类号： H03H9/13

    CPC分类号： H03H19/004 ,  H03H9/02007 ,  H03H2009/02204

    摘要： Disclosed is a system and method for controlling a resonance frequency of a Film Bulk Acoustic Resonator (FBAR) device. The system includes at least one switching capacitor coupled to the FBAR device and a modulator. The at least one switching capacitor includes at least one capacitor and a switch configuration disposed in series with the FBAR device and the at least one capacitor, which is switch configuration capable of opening and closing connection of the at least one capacitor with the FBAR device. The modulator is coupled to the switch configuration, which generates a switching condition signal based on the manufacturing variation in the FBAR device and the environmental effects on the FBAR device. The switch configuration performs opening and closing of the connection of the at least one capacitor and the FBAR device based on the switching condition signal.

    摘要翻译： 公开了一种用于控制膜体声波谐振器（FBAR）装置的谐振频率的系统和方法。 该系统包括耦合到FBAR器件和调制器的至少一个开关电容器。 所述至少一个开关电容器包括至少一个电容器和与所述FBAR器件和所述至少一个电容器串联布置的开关配置，所述至少一个电容器是能够打开和关闭所述至少一个电容器与所述FBAR器件的连接的开关配置。 调制器耦合到开关配置，其根据FBAR器件的制造变化和对FBAR器件的环境影响产生开关条件信号。 开关配置基于开关条件信号来执行至少一个电容器和FBAR器件的连接的打开和闭合。

    Single event upset hardened latch
    7.
    发明授权
    Single event upset hardened latch 有权
    单个事件镦粗硬化闩锁

    公开(公告)号：US07161404B2

    公开(公告)日：2007-01-09

    申请号：US10742436

    申请日：2003-12-19

    申请人： Peter Hazucha ,  Krishnamurthy Soumyanath

    发明人： Peter Hazucha ,  Krishnamurthy Soumyanath

    IPC分类号： H03K3/289

    CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/0375 ,  H03K3/356173

    摘要： A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

    摘要翻译： 公开了一种能够提供针对单个事件扰乱（SEU）的保护的硬化锁存器。 硬化的锁存器包括第一锁存器和第二锁存器，其对第一锁存器的门的子集进行镜像。 第二锁存器插入在第一锁存器的保持器电路的反馈路径中，并且与第一锁存器的保持器电路的栅极交叉耦合。 如果连续的SEU之间的时间大于锁存器的恢复时间，则锁存器会针对单个事件扰乱和任意数量的连续的SEU进行加固。 硬化锁存器的替代实施例包括分离缓冲器输出。 该实施例能够减少错误瞬变的传播。 硬化锁存器的另一替代实施例包括米勒C缓冲器输出。 该实施例能够将错误瞬变的传播降低到使用分离缓冲器输出的硬化锁存器中可实现的电平以下。

    Domino circuits with high performance and high noise immunity
    9.
    发明授权
    Domino circuits with high performance and high noise immunity 有权
    具有高性能和高抗噪声能力的多米诺电路

    公开(公告)号：US06204696B1

    公开(公告)日：2001-03-20

    申请号：US09158410

    申请日：1998-09-22

    申请人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

    发明人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is also coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provide therefrom an evaluated output signal. In other embodiments, the invention includes a domino circuit having a predischarge circuit coupled to a domino stage conductor. An evaluation path circuit includes source follower nFET devices coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provides therefrom an evaluated output signal. In still other embodiments, the invention includes a domino circuit having a precharge circuit including coupled to a domino stage conductor. An evaluation path circuit is coupled to the domino stage conductor. An output stage includes an inverter to receive a signal from the domino stage conductor and to provide an evaluated output signal on an output conductor, the output stage including a duplicate evaluation path circuit coupled to an output conductor.

    摘要翻译： 在一些实施例中，本发明包括具有预充电电路的多米诺骨牌电路，该预充电电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。 评估路径电路也耦合到多米诺骨牌导体。 迟滞输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。 在其他实施例中，本发明包括具有耦合到多米诺骨牌导体的预放电电路的多米诺骨牌电路。 评估路径电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。 滞后输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。 在其他实施例中，本发明包括具有预充电电路的多米诺骨牌电路，其包括耦合到多米诺骨牌导体。 评估路径电路耦合到多米诺骨牌导体。 输出级包括反相器，用于从多米诺骨架导体接收信号并在输出导体上提供评估输出信号，输出级包括耦合到输出导体的重复评估路径电路。