发明授权
- 专利标题: Semiconductor device and a process for designing a mask
- 专利标题(中): 半导体器件和设计掩模的工艺
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申请号: US09340697申请日: 1999-06-29
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公开(公告)号: US06396158B1公开(公告)日: 2002-05-28
- 发明人: Edward O. Travis , Aykut Dengi , Sejal Chheda , Tat-Kwan Yu , Mark S. Roberton , Ruiqi Tian
- 申请人: Edward O. Travis , Aykut Dengi , Sejal Chheda , Tat-Kwan Yu , Mark S. Roberton , Ruiqi Tian
- 主分类号: H01L2348
- IPC分类号: H01L2348
摘要:
Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).