Invention Grant
- Patent Title: Method of fabricating reduced critical dimension for conductive line and space
- Patent Title (中): 制造导电线和空间的关键尺寸的方法
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Application No.: US09384013Application Date: 1999-08-26
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Publication No.: US06399286B1Publication Date: 2002-06-04
- Inventor: Yuan-Hung Liu , Bor-Wen Chan
- Applicant: Yuan-Hung Liu , Bor-Wen Chan
- Priority: TW88110532 19990623
- Main IPC: G03F736
- IPC: G03F736

Abstract:
A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.
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