公开(公告)号：US08513107B2

公开(公告)日：2013-08-20

申请号：US12693504

申请日：2010-01-26

申请人： Bor-Wen Chan ,  Fang Wen Tsai

发明人： Bor-Wen Chan ,  Fang Wen Tsai

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66795 ,  H01L29/66545

摘要： A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.

摘要翻译： 提供了用于替代金属栅极技术的结构和方法，用于与半导体鳍片或其它器件结合使用。 通过去除诸如多晶硅的牺牲栅极材料在电介质中形成开口。 在其中形成晶体管沟道的半导体鳍片的表面在开口中露出。 通过在开口内部和栅极电介质材料上形成扩散阻挡层形成替代金属栅极，扩散阻挡层形成有利地进行原位等离子体处理操作。 处理操作利用氩和氢中的至少一种，并固化扩散阻挡层中的表面缺陷，使得扩散阻挡层能够形成较小的厚度。 处理操作降低电阻率，致密化并改变扩散阻挡层的原子比，随后进行金属沉积。

公开(公告)号：US20110241130A1

公开(公告)日：2011-10-06

申请号：US12753372

申请日：2010-04-02

申请人： Bor-Wen CHAN ,  Hsueh Wen Tsau

发明人： Bor-Wen CHAN ,  Hsueh Wen Tsau

IPC分类号： H01L29/78 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3205

CPC分类号： H01L29/401 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/67207 ,  H01L21/76846 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.

摘要翻译： 半导体器件包括在金属层和至少一个下层之间的阻挡结构。 阻挡结构具有被配置为防止金属从金属层扩散到至少一个下层中的第一层，以及被配置用于增强半导体器件的电性能的第二层。

公开(公告)号：US20110027958A1

公开(公告)日：2011-02-03

申请号：US12904809

申请日：2010-10-14

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L21/336

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US07241674B2

公开(公告)日：2007-07-10

申请号：US10846278

申请日：2004-05-13

申请人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC分类号： H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

摘要翻译： 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US20060040481A1

公开(公告)日：2006-02-23

申请号：US10919571

申请日：2004-08-17

申请人： Bor-Wen Chan ,  Yu-Shen Lai

发明人： Bor-Wen Chan ,  Yu-Shen Lai

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L29/66507 ,  H01L29/6656

摘要： Methods and structures for preventing salicidation are disclosed. A substrate has an gate electrode on it. Spacers are on sidewalls of the gate electrode, exposing a top portion of the gate electrode. A dielectric layer is formed above the spacers, covering the exposed top portion of the gate electrode. Methods and structures for forming source and drain salicidation are disclosed. They further salicidize source and drain regions which are adjacent to the spacers without forming salicidation on the gate electrode while salicidizing the source and drain regions. Methods and structures for forming gate electrode salicidation are also disclosed. They further form another dielectric layer covering the salicidized source and drain regions. A portion of the dielectric layer is removed so as to expose a top surface of the gate electrode. The gate electrode is then salicidized.

摘要翻译： 公开了防止盐化的方法和结构。 衬底上具有栅电极。 隔板位于栅电极的侧壁上，露出栅电极的顶部。 在间隔物的上方形成介电层，覆盖露出的栅电极顶部。 公开了用于形成源极和漏极盐析的方法和结构。 它们进一步对与间隔物相邻的源极和漏极区域进行盐化，而不会在栅电极上形成水化，同时对源极和漏极区域进行盐化。 还公开了形成栅电极盐析的方法和结构。 它们进一步形成覆盖水化源极和漏极区域的另一个介电层。 去除电介质层的一部分以露出栅电极的顶表面。 然后将栅电极进行水杨酸化。

公开(公告)号：US20050179098A1

公开(公告)日：2005-08-18

申请号：US10780513

申请日：2004-02-17

申请人： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

摘要： A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

摘要翻译： 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。

公开(公告)号：US20050121750A1

公开(公告)日：2005-06-09

申请号：US10728995

申请日：2003-12-05

申请人： Bor-Wen Chan ,  Yu-I Wang ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Yu-I Wang ,  Han-Jan Tao

IPC分类号： H01L21/033 ,  H01L21/336 ,  H01L23/58

CPC分类号： H01L29/4983 ,  H01L21/0337 ,  H01L29/6653 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

摘要翻译： 一种制造微电子器件的方法，包括在衬底上形成图案化特征，并使用含氟等离子体源将图形化特征和衬底上的共形聚合物层沉积。 蚀刻聚合物层以暴露图案化特征和基底的一部分，由此在图案化特征的相对侧上形成聚合物间隔物。

公开(公告)号：US06764903B1

公开(公告)日：2004-07-20

申请号：US10427451

申请日：2003-04-30

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21336

CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.

摘要翻译： 从覆盖目标层形成图案化目标层的方法采用层叠在覆盖目标层上的一对覆盖层硬掩模层。 在其上形成图案化的第三掩模层。 该方法还采用四个独立的蚀刻步骤。 一个蚀刻步骤是用于从橡皮布上面的硬掩模层形成图案化的上卧硬掩模层的各向异性蚀刻步骤。 然后在第二蚀刻步骤中各向同性蚀刻图案化的上卧硬掩模层，以形成各向同性蚀刻的图案化的上面的硬掩模层。 该方法对于形成半导体产品中线宽减小和尺寸控制增强的栅电极特别有用。

公开(公告)号：US06399286B1

公开(公告)日：2002-06-04

申请号：US09384013

申请日：1999-08-26

申请人： Yuan-Hung Liu ,  Bor-Wen Chan

发明人： Yuan-Hung Liu ,  Bor-Wen Chan

IPC分类号： G03F736

CPC分类号： H01L21/32139 ,  H01L21/76838 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.

摘要翻译： 描述了用于降低导电线的临界尺寸和空间的制造方法，其中导电层和掩模层依次形成在基板上。 进行锥形蚀刻以形成多个第一开口，其中开口的横截面从顶部到底部逐渐变细，并暴露导电层的表面。 形成与掩模层类似的高度的平坦化牺牲层，覆盖导电层的暴露表面。 在暴露的掩模层上进一步进行第二锥形腐蚀以形成多个第二开口，其中开口的横截面从顶部到底部逐渐变细。 然后去除牺牲层。 此后，使用掩模层作为硬掩模，在暴露的导电层上进行各向异性蚀刻，以形成多条导线，然后除去掩模层。

公开(公告)号：US08093117B2

公开(公告)日：2012-01-10

申请号：US12687714

申请日：2010-01-14

申请人： Hsueh Wen Tsau ,  Kuang-Yuan Hsu ,  Bor-Wen Chan

发明人： Hsueh Wen Tsau ,  Kuang-Yuan Hsu ,  Bor-Wen Chan

IPC分类号： H01L21/338

CPC分类号： H01L21/28088 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供基板。 在基板上形成虚拟栅极。 在虚拟栅极周围形成电介质材料。 然后去除伪栅极以在电介质材料中形成开口。 此后，形成功函数金属层以部分地填充开口。 然后使用多晶硅替代方法和旋涂方法之一用导电层填充开口的剩余部分。