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    Method of fabricating reduced critical dimension for conductive line and space
    1.
    发明授权
    Method of fabricating reduced critical dimension for conductive line and space 有权
    制造导电线和空间的关键尺寸的方法

    公开(公告)号：US06399286B1

    公开(公告)日：2002-06-04

    申请号：US09384013

    申请日：1999-08-26

    Applicant: Yuan-Hung Liu ,  Bor-Wen Chan

    Inventor： Yuan-Hung Liu ,  Bor-Wen Chan

    IPC: G03F736

    CPC classification number: H01L21/32139 ,  H01L21/76838 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.

    Abstract translation: 描述了用于降低导电线的临界尺寸和空间的制造方法，其中导电层和掩模层依次形成在基板上。 进行锥形蚀刻以形成多个第一开口，其中开口的横截面从顶部到底部逐渐变细，并暴露导电层的表面。 形成与掩模层类似的高度的平坦化牺牲层，覆盖导电层的暴露表面。 在暴露的掩模层上进一步进行第二锥形腐蚀以形成多个第二开口，其中开口的横截面从顶部到底部逐渐变细。 然后去除牺牲层。 此后，使用掩模层作为硬掩模，在暴露的导电层上进行各向异性蚀刻，以形成多条导线，然后除去掩模层。

    Method for forming pullback opening above shallow trenc isolation structure
    2.
    发明授权
    Method for forming pullback opening above shallow trenc isolation structure 有权
    在浅沟隔离结构上方形成回拉开口的方法

    公开(公告)号：US06291312B1

    公开(公告)日：2001-09-18

    申请号：US09395108

    申请日：1999-09-14

    Applicant: Bor-Wen Chan ,  Yuan-Hung Liu

    Inventor： Bor-Wen Chan ,  Yuan-Hung Liu

    IPC: H01L2176

    CPC classification number: H01L21/76224

    Abstract: A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.

    Abstract translation: 一种用于在浅沟槽隔离结构上形成回拉开口的方法。 在衬底上形成图案化掩模层。 牺牲层形成在掩模层的侧壁上。 蚀刻衬底的暴露部分以在衬底中形成沟槽。 去除牺牲层以增加沟槽上方的开口的宽度。

    Method of manufacturing double-recess crown-shaped DRAM capacitor
    3.
    发明授权
    Method of manufacturing double-recess crown-shaped DRAM capacitor 有权
    制造双凹冠状DRAM电容器的方法

    公开(公告)号：US06232175B1

    公开(公告)日：2001-05-15

    申请号：US09466044

    申请日：1999-12-17

    Applicant: Yuan-Hung Liu ,  Bor-Wen Chan

    Inventor： Yuan-Hung Liu ,  Bor-Wen Chan

    IPC: H01L218242

    CPC classification number: H01L28/92 ,  H01L21/32139 ,  H01L27/10852

    Abstract: A double recess crown-shaped DRAM capacitor is formed in a simplified process. A dielectric layer is formed over a substrate. Using photolithographic and etching techniques, a contact opening is formed in the dielectric layer. A conductive layer is formed over the dielectric layer filling the contact opening to form a conductive plug. A second dielectric layer is formed over the conductive layer. Again using photolithographic and etching techniques, the second dielectric layer is patterned to form a trapezoidal-shaped dielectric layer. An organic bottom anti-reflective coating (organic BARC) is coated over the trapezoidal-shaped dielectric layer and the conductive layer. Organic BARC above the trapezoidal-shaped dielectric layer is removed. Using the organic BARC as an etching mask, the trapezoidal-shaped dielectric layer is etched to form triangular-shaped dielectric layers and a trench in the conductive layer. The residual organic BARC is completely removed. Using the triangular-shaped dielectric layers as a hard etching mask, two types of trenches each having a different depth are formed in the conductive layer. The triangular-shaped dielectric layers are removed to form a double-recess lower electrode. Hemispherical silicon grains are grown over the interior surface of the double-recess lower electrode as well as the external sidewalls. Finally, a conformal dielectric layer and a conformal conductive layer are sequentially formed over the surface of the double-recess lower electrode.

    Abstract translation: 以简化的工艺形成双凹槽冠状DRAM电容器。 介电层形成在衬底上。 使用光刻和蚀刻技术，在电介质层中形成接触开口。 在填充接触开口的电介质层上形成导电层以形成导电插塞。 在导电层上形成第二介电层。 再次使用光刻和蚀刻技术，将第二介电层图案化以形成梯形介电层。 将有机底部抗反射涂层（有机BARC）涂覆在梯形介电层和导电层上。 去除梯形介电层上方的有机BARC。 使用有机BARC作为蚀刻掩模，蚀刻梯形介电层以在导电层中形成三角形介电层和沟槽。 残留的有机BARC被完全去除。 使用三角形介电层作为硬蚀刻掩模，在导电层中形成各具有不同深度的两种类型的沟槽。 去除三角形电介质层以形成双凹槽下电极。 半球状硅晶粒生长在双凹槽下电极的内表面以及外侧壁上。 最后，在双凹槽下电极的表面上依次形成保形电介质层和保形导电层。

    Method of fabricating a borderless via
    4.
    发明授权
    Method of fabricating a borderless via 有权
    制造无边界通孔的方法

    公开(公告)号：US06352919B1

    公开(公告)日：2002-03-05

    申请号：US09620033

    申请日：2000-07-20

    Applicant: Yeur-Luen Tu ,  Bor-Wen Chan ,  Yuan-Hung Liu

    Inventor： Yeur-Luen Tu ,  Bor-Wen Chan ,  Yuan-Hung Liu

    IPC: H01L214763

    CPC classification number: H01L21/76802 ,  H01L21/76801

    Abstract: A method of fabricating a borderless via is disclosed. A semiconductor substrate having a first dielectric layer thereon is provided. Next, a first conductive structure and a second conductive structure whose area is much smaller than said first conductive structure are formed on said first dielectric layer. After that, a second dielectric layer with an uneven surface is formed. Then, a planarizing layer is coated over said second dielectric layer to fill said uneven surface. Next, an etch back process is used to create a etching stop layer consisting of a portion of second dielectric layer. Subsequently, a third dielectric layer is formed over said second dielectric layer followed by selectively etching said third dielectric layer until said second dielectric layer is exposed to create a borderless via.

    Abstract translation: 公开了制造无边界通孔的方法。 提供其上具有第一介电层的半导体衬底。 接下来，在所述第一介电层上形成面积比所述第一导电结构小得多的第一导电结构和第二导电结构。 之后，形成具有不平坦表面的第二电介质层。 然后，在所述第二电介质层上涂覆平坦化层以填充所述不平坦表面。 接下来，使用回蚀工艺来产生由第二介电层的一部分组成的蚀刻停止层。 随后，在所述第二电介质层上形成第三电介质层，随后选择性地蚀刻所述第三电介质层，直到所述第二电介质层暴露以形成无边界通孔。

    Method of fabricating transistor
    5.
    发明授权
    Method of fabricating transistor 有权
    制造晶体管的方法

    公开(公告)号：US06218244B1

    公开(公告)日：2001-04-17

    申请号：US09482757

    申请日：2000-01-13

    Applicant: Bor-Wen Chan ,  Yuan-Hung Liu

    Inventor： Bor-Wen Chan ,  Yuan-Hung Liu

    IPC: H01L218242

    CPC classification number: H01L28/92 ,  H01L27/10852

    Abstract: A method of manufacturing a DRAM capacitor is described. A silicon substrate structure includes an oxide layer over a substrate and a polysilicon layer over the oxide layer. The polysilicon layer also includes a plug that penetrates the oxide layer. A patterned photoresist layer is next formed over the polysilicon layer. Spacers having a low etching rate are formed on the sidewalls of the photoresist layer by carrying out a chemical reaction next to the sidewall of the photoresist layer. A dry etching operation is carried out to etch the unreacted photoresist layer and the polysilicon layer exposed by the openings in the photoresist layer. Using the spacers as an etching mask, a portion of the polysilicon layer under the photoresist layer is removed by continuing the dry etching operation. Lastly, the spacers are removed to form a crown-shaped capacitor.

    Abstract translation: 描述制造DRAM电容器的方法。 硅衬底结构包括在衬底上的氧化物层和氧化物层上的多晶硅层。 多晶硅层还包括穿透氧化物层的插塞。 随后在多晶硅层上形成图案化的光致抗蚀剂层。 通过在光致抗蚀剂层的侧壁附近进行化学反应，在光致抗蚀剂层的侧壁上形成具有低蚀刻速率的间隔物。 进行干蚀刻操作以蚀刻由光致抗蚀剂层中的开口暴露的未反应的光致抗蚀剂层和多晶硅层。 使用间隔物作为蚀刻掩模，通过继续干蚀刻操作来除去光致抗蚀剂层下面的多晶硅层的一部分。 最后，去除间隔物以形成冠状电容器。

    Image sensor having enhanced backside illumination quantum efficiency
    7.
    发明授权
    Image sensor having enhanced backside illumination quantum efficiency 有权
    具有增强的背面照明量子效率的图像传感器

    公开(公告)号：US09041841B2

    公开(公告)日：2015-05-26

    申请号：US12557154

    申请日：2009-09-10

    Applicant: Yin-Kai Liao ,  Han-Chi Liu ,  Yuan-Hung Liu ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    Inventor： Yin-Kai Liao ,  Han-Chi Liu ,  Yuan-Hung Liu ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    IPC: H04N3/14 ,  H04N5/335 ,  H01L27/146

    CPC classification number: H01L27/14629 ,  H01L21/76829 ,  H01L21/76831 ,  H01L27/14603 ,  H01L27/14614 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14683 ,  H01L27/14685 ,  H04N3/155

    Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.

    Abstract translation: 公开了一种用于图像感测的系统和方法。 实施例包括具有像素区域和逻辑区域的基板。 在像素区域上形成第一抗蚀保护氧化物（RPO），但不在逻辑区域上。 硅化物接触形成在像素区域中形成的有源器件的顶部上，而不是在像素区域中的衬底的表面上，并且在有源器件的顶部和衬底的表面上形成硅化物接触 逻辑区域。 在像素区域和逻辑区域上形成第二RPO，并且在第二RPO上形成接触蚀刻停止层。 当光从基板的背面入射传感器时，这些层有助于将光反射回图像传感器，并且还有助于防止由过蚀刻引起的损坏。

    Magnetic memory cells and manufacturing methods
    9.
    发明申请
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号：US20070096230A1

    公开(公告)日：2007-05-03

    申请号：US11610760

    申请日：2006-12-14

    Applicant: Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    Inventor： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    IPC: H01L43/00 ,  H01L29/82

    CPC classification number: H01L43/12 ,  H01L27/228

    Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    Abstract translation: 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。

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