Invention Grant
- Patent Title: Apparatus for and method of detecting a delay fault in a phase-locked loop circuit
- Patent Title (中): 检测锁相环电路延时故障的装置及方法
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Application No.: US09494321Application Date: 2000-01-28
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Publication No.: US06400129B1Publication Date: 2002-06-04
- Inventor: Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
- Applicant: Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
- Main IPC: G01R2500
- IPC: G01R2500

Abstract:
There is provided a method and an apparatus for detecting a delay fault in a phase-locked loop circuit. A frequency impulse is applied to the PLL circuit under test as a reference clock, and a waveform of a signal outputted from the PLL circuit under test is transformed to an analytic signal to estimate its instantaneous phase. A linear phase is estimated from the estimated instantaneous phase, and the estimated linear phase is removed from the estimated instantaneous phase to obtain a fluctuation term of the instantaneous phase. A delay fault is detected by comparing a time duration during which the PLL circuit stays in a state of oscillating a certain frequency with the time duration during which a fault-free PLL circuit stays in a state of oscillating a certain frequency.
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