发明授权
US06410399B1 Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization
失效
通过硅化法降低基于沟槽的DRAMS中的带，字线和位线接触电阻的工艺
- 专利标题： Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization
- 专利标题（中）： 通过硅化法降低基于沟槽的DRAMS中的带，字线和位线接触电阻的工艺
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申请号： US09606493申请日： 2000-06-29
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公开(公告)号： US06410399B1公开(公告)日： 2002-06-25
- 发明人: Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
- 申请人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
- 主分类号： H01L2120
- IPC分类号： H01L2120
摘要：
A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.
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