发明授权
US06436749B1 Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion
失效
用于使用受控栅极耗尽的CMOS器件形成混合高压(HV / LV)晶体管的方法
- 专利标题: Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion
- 专利标题(中): 用于使用受控栅极耗尽的CMOS器件形成混合高压(HV / LV)晶体管的方法
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申请号: US09658655申请日: 2000-09-08
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公开(公告)号: US06436749B1公开(公告)日: 2002-08-20
- 发明人: William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
- 申请人: William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
- 主分类号: H01L218238
- IPC分类号: H01L218238
摘要:
A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.
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