发明授权
US06438653B1 Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system
有权
高速缓存存储器控制电路包括总结高速缓存标签存储器并行处理器系统中的缓存标签信息
- 专利标题： Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system
- 专利标题（中）： 高速缓存存储器控制电路包括总结高速缓存标签存储器并行处理器系统中的缓存标签信息
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申请号： US09330981申请日： 1999-06-14
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公开(公告)号： US06438653B1公开(公告)日： 2002-08-20
- 发明人: Hideya Akashi , Toshio Okochi , Toru Shonai , Masamori Kashiyama
- 申请人： Hideya Akashi , Toshio Okochi , Toru Shonai , Masamori Kashiyama
- 优先权： JP10-185643 19980616
- 主分类号： G06F1206
- IPC分类号： G06F1206
摘要：
A multi-processor system includes a plurality of processor node control circuits in respective processor nodes, and a cache memory which is an external cache. Each of the processor node control circuits includes a summarized cache tag memory for storing “summarized information” which is information having a reduced number of bits by summarizing information on a cache tag portion in the cache memory and indicating whether each of blocks is effectively indexed in the cache tag portion. For cache coherence control, the summarized cache tag memory is first accessed, so that the cache tag portion is accessed only when it is determined that a target block is effectively indexed, to determine whether the cache coherence control for the node is required.
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