- 专利标题: Method for making a dual damascene interconnect using a multilayer hard mask
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申请号: US09746035申请日: 2000-12-22
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公开(公告)号: US06479391B2公开(公告)日: 2002-11-12
- 发明人: Patrick Morrow , Jihperng Leu , Chia-Hong Jan
- 申请人: Patrick Morrow , Jihperng Leu , Chia-Hong Jan
- 主分类号: H01L21302
- IPC分类号: H01L21302
摘要:
An improved method for making a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A layer of photoresist is deposited and patterned to expose part of the second hard masking layer to define a via. That exposed part of the second hard masking layer is then etched. A second layer of photoresist is deposited and patterned to expose a second part of the second hard masking layer to define a trench. After etching the exposed second part of the second hard masking layer, a via and trench are etched into the dielectric layer, which are then filled with a conductive material.
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