公开(公告)号：US20240161817A1

公开(公告)日：2024-05-16

申请号：US17985753

申请日：2022-11-11

Applicant: Charles Augustine ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah

Inventor： Charles Augustine ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104

Abstract: Embodiments herein relate to a three-transistor gain cell which is provided using a complementary field-effect transistor device to achieve scaling. The cell includes an n-type layer arranged above a p-type layer. In one implementation, two nMOS transistors are arranged above one pMOS transistor and a conductive path is provided to connect the gate of one of the nMOS transistors to a storage node in the p-type layer, where the storage node is coupled to a drain of the pMOS transistor. In another implementation, one nMOS transistor is arranged above two pMOS transistors and a conductive path is provided to connect the gate of one of the pMOS transistors to a storage node in the n-type layer, where the storage node is coupled to a source of the nMOS transistor.

公开(公告)号：US09646972B2

公开(公告)日：2017-05-09

申请号：US14912402

申请日：2013-09-25

Applicant: Rajashree Baskaran ,  Kimin Jun ,  Patrick Morrow

Inventor： Rajashree Baskaran ,  Kimin Jun ,  Patrick Morrow

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L27/10832 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1087 ,  H01L28/20 ,  H01L28/87 ,  H01L28/91 ,  H01L29/945

Abstract: Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

公开(公告)号：US09420707B2

公开(公告)日：2016-08-16

申请号：US12653722

申请日：2009-12-17

Applicant: Qing Ma ,  Chuan Hu ,  Patrick Morrow

Inventor： Qing Ma ,  Chuan Hu ,  Patrick Morrow

IPC: H05K1/11 ,  H05K3/46 ,  H01L23/498 ,  H05K3/42

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的基板的实施例。 衬底包括由已经结合在一起的两个或更多个离散的玻璃层组成的芯。 可以在相邻的玻璃层之间设置单独的粘合层，以将这些层连接在一起。 衬底还可以包括在多层玻璃芯的相对侧上或者可能在芯的一侧上的堆积结构。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸通过多层玻璃芯，并且一个或多个导体可以与布置在芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：US20160197069A1

公开(公告)日：2016-07-07

申请号：US14778512

申请日：2013-06-25

Applicant: Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L27/06 ,  H01L29/78 ,  H01L23/538 ,  H01L27/11 ,  H01L21/822

CPC classification number: H01L27/0688 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

Abstract translation: 使用一个或多个本地级间互连的单片3D IC，其与3D IC内的至少一个晶体管级上的至少一个晶体管的至少一个结构紧密集成。 在某些实施例中，局部级间互连与至少一个晶体管的栅电极或源/漏区相交，并延伸穿过设置在3D IC中的第一和第二晶体管级之间的至少一个级间介电层。 有利地，本地级间互连可以在3D IC的不同级别中的晶体管之间进行直接垂直连接，而不会横向绕过互连的上覆或下伏晶体管级的覆盖区（即，横向或平面区域）。

公开(公告)号：US08637778B2

公开(公告)日：2014-01-28

申请号：US12756748

申请日：2010-04-08

Applicant: Qing Ma ,  Jun He ,  Patrick Morrow ,  Paul B. Fischer ,  Sridhar Balakrishnan ,  Satish Radhakrishnan ,  Tatyana Tanya Andryushchenko ,  Guanghai Xu

Inventor： Qing Ma ,  Jun He ,  Patrick Morrow ,  Paul B. Fischer ,  Sridhar Balakrishnan ,  Satish Radhakrishnan ,  Tatyana Tanya Andryushchenko ,  Guanghai Xu

IPC: H05K1/03 ,  H05K7/02

CPC classification number: H01L24/19 ,  B23K1/0016 ,  H01L21/0334 ,  H01L24/11 ,  H01L2224/245 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/4015 ,  H05K2201/1028 ,  H01L2924/00

Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

Abstract translation: 本主题涉及制造微电子器件的领域。 在至少一个实施例中，本主题涉及形成具有其部分的互连，其在附接到外部设备之后在冷却期间从微电子器件脱粘。 脱粘部分允许互连件弯曲并吸收应力。

公开(公告)号：US08421225B2

公开(公告)日：2013-04-16

申请号：US13470822

申请日：2012-05-14

Applicant: Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Y. Chan ,  Mauro J. Kobrinsky ,  Sarah E. Kim ,  Kevin P. O'Brien ,  Michael C. Harmes ,  Thomas Marieb

Inventor： Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Y. Chan ,  Mauro J. Kobrinsky ,  Sarah E. Kim ,  Kevin P. O'Brien ,  Michael C. Harmes ,  Thomas Marieb

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

公开(公告)号：US08203208B2

公开(公告)日：2012-06-19

申请号：US13103267

申请日：2011-05-09

Applicant: Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Y. Chan ,  Mauro J. Kobrinsky ,  Sarah E. Kim ,  Kevin P. O'Brien ,  Michael C. Harmes ,  Thomas Marieb

Inventor： Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Y. Chan ,  Mauro J. Kobrinsky ,  Sarah E. Kim ,  Kevin P. O'Brien ,  Michael C. Harmes ,  Thomas Marieb

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract translation: 具有可靠接合和衬底保护的三维堆叠衬底布置。

公开(公告)号：US07973407B2

公开(公告)日：2011-07-05

申请号：US12319035

申请日：2008-12-31

Applicant: Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Y. Chan ,  Mauro J. Kobrinsky ,  Sarah E. Kim ,  Kevin P. O'Brien ,  Michael C. Harmes ,  Thomas Marieb

Inventor： Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Y. Chan ,  Mauro J. Kobrinsky ,  Sarah E. Kim ,  Kevin P. O'Brien ,  Michael C. Harmes ,  Thomas Marieb

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract translation: 具有可靠接合和衬底保护的三维堆叠衬底布置。

公开(公告)号：US07436035B2

公开(公告)日：2008-10-14

申请号：US10917722

申请日：2004-08-12

Applicant: Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

Inventor： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC: H01L29/72

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

Abstract translation: 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

公开(公告)号：US07402509B2

公开(公告)日：2008-07-22

申请号：US11081187

申请日：2005-03-16

Applicant: Mauro J. Kobrinsky ,  Jun He ,  Kevin O'Brien ,  Patrick Morrow ,  Ying Zhou ,  Shriram Ramanathan

Inventor： Mauro J. Kobrinsky ,  Jun He ,  Kevin O'Brien ,  Patrick Morrow ,  Ying Zhou ,  Shriram Ramanathan

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L21/76867 ,  B23K35/302 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76888 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/48 ,  H01L2924/013

Abstract: A method of forming self-passivating interconnects. At least one of two mating bond structures is formed, at least in part, from an alloy of a first metal and a second metal (or other element). The second metal is capable of migrating through the first metal to free surfaces of the mating bond structures. During bonding, the two mating bond structures are bonded together to form an interconnect, and the second metal segregates to free surfaces of this interconnect to form a passivation layer. Other embodiments are described and claimed.

Abstract translation: 一种形成自钝化互连的方法。 至少部分地由第一金属和第二金属（或其它元素）的合金形成两个匹配结合结构中的至少一个。 第二金属能够通过第一金属迁移到配合结合结构的自由表面。 在接合期间，两个配对结合结构结合在一起以形成互连，并且第二金属分离到该互连的自由表面以形成钝化层。 描述和要求保护其他实施例。