Invention Grant
- Patent Title: Method of fabricating a trench isolation structure having sidewall oxide layers with different thicknesses
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Application No.: US09933039Application Date: 2001-08-21
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Publication No.: US06486039B2Publication Date: 2002-11-26
- Inventor: Jae-yoon Yoo , Jeong-soo Lee , Nae-in Lee
- Applicant: Jae-yoon Yoo , Jeong-soo Lee , Nae-in Lee
- Priority: KR00-84160 20001228
- Main IPC: H01L21302
- IPC: H01L21302

Abstract:
A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.
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