公开(公告)号：US09537009B2

公开(公告)日：2017-01-03

申请号：US14955289

申请日：2015-12-01

申请人： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

摘要翻译： 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US09520497B2

公开(公告)日：2016-12-13

申请号：US14951932

申请日：2015-11-25

申请人： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US20160293484A1

公开(公告)日：2016-10-06

申请号：US15000302

申请日：2016-01-19

申请人： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

发明人： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

IPC分类号： H01L21/768

CPC分类号： H01L21/76882 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

摘要： In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

摘要翻译： 在形成布线结构的方法中，在基板上形成下部结构。 在下部结构上形成绝缘中间层。 部分去除绝缘中间层以形成至少一个通孔和虚拟通孔。 绝缘中间层的上部被部分地去除以形成连接通孔和虚拟通孔的沟槽。 形成填充通孔和虚拟通孔的第一金属层。 填充沟槽的第二金属层形成在第一金属层上。

公开(公告)号：US20160276267A1

公开(公告)日：2016-09-22

申请号：US15018484

申请日：2016-02-08

申请人： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Nae-In Lee ,  Jeong-Ok Cha ,  Jung-Ha Hwang

发明人： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Nae-In Lee ,  Jeong-Ok Cha ,  Jung-Ha Hwang

IPC分类号： H01L23/522 ,  H01L21/285 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53238

摘要： Methods of forming wiring structures and methods of manufacturing semiconductor devices include forming a lower structure on a substrate, forming an interlayer insulating film including an opening on the lower structure, forming a liner film on an inner surface of the opening, treating a surface of the liner film by an ion bombardment, and forming a first conductive film on the liner film. The first conductive film is formed to be at least partially filled in the opening through a reflow process. Related wiring structures and semiconductor devices are also discussed.

摘要翻译： 形成布线结构的方法和制造半导体器件的方法包括在基板上形成下部结构，在下部结构上形成包括开口的层间绝缘膜，在开口的内表面上形成衬垫膜， 通过离子轰击形成衬垫膜，并在衬垫膜上形成第一导电膜。 第一导电膜通过回流工艺形成为至少部分地填充在开口中。 还讨论了相关的布线结构和半导体器件。

公开(公告)号：US20160087101A1

公开(公告)日：2016-03-24

申请号：US14955289

申请日：2015-12-01

申请人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

发明人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

摘要翻译： 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US09257520B2

公开(公告)日：2016-02-09

申请号：US14680349

申请日：2015-04-07

申请人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

发明人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US09129952B2

公开(公告)日：2015-09-08

申请号：US14033718

申请日：2013-09-23

申请人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

发明人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

摘要翻译： 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

公开(公告)号：US09024385B2

公开(公告)日：2015-05-05

申请号：US14033718

申请日：2013-09-23

申请人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

发明人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/66

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US20110198710A1

公开(公告)日：2011-08-18

申请号：US13039811

申请日：2011-03-03

申请人： Jong-Ho LEE ,  Nae-In LEE

发明人： Jong-Ho LEE ,  Nae-In LEE

IPC分类号： H01L29/772 ,  H01L29/06

CPC分类号： H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

摘要： A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

摘要翻译： 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US07902609B2

公开(公告)日：2011-03-08

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L23/62

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。