Invention Grant
- Patent Title: Method and apparatus for synthesizing levelized logic
- Patent Title (中): 用于合成等级化逻辑的方法和装置
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Application No.: US09833413Application Date: 2001-04-12
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Publication No.: US06502224B2Publication Date: 2002-12-31
- Inventor: Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
- Applicant: Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
- Main IPC: G06F1750
- IPC: G06F1750

Abstract:
A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.
Public/Granted literature
- US20020152450A1 METHOD AND APPARATUS FOR SYNTHESIZING LEVELIZED LOGIC Public/Granted day:2002-10-17
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