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US06502224B2 Method and apparatus for synthesizing levelized logic 失效
用于合成等级化逻辑的方法和装置

Method and apparatus for synthesizing levelized logic
Abstract:
A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.
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