发明授权
US06507067B1 Flash EEPROM with integrated device for limiting the erase source voltage
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具有集成器件的闪存EEPROM,用于限制擦除源电压
- 专利标题: Flash EEPROM with integrated device for limiting the erase source voltage
- 专利标题(中): 具有集成器件的闪存EEPROM,用于限制擦除源电压
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申请号: US08692936申请日: 1996-07-31
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公开(公告)号: US06507067B1公开(公告)日: 2003-01-14
- 发明人: Lorenzo Fratin , Leonardo Ravazzi , Carlo Riva
- 申请人: Lorenzo Fratin , Leonardo Ravazzi , Carlo Riva
- 优先权: EP95830351 19950802
- 主分类号: H01L29788
- IPC分类号: H01L29788
摘要:
A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.
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