公开(公告)号：US5920776A

公开(公告)日：1999-07-06

申请号：US712373

申请日：1996-09-11

申请人： Lorenzo Fratin ,  Leonardo Ravazzi ,  Carlo Riva

发明人： Lorenzo Fratin ,  Leonardo Ravazzi ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L29/1045 ,  H01L29/7881

摘要： A nonvolatile memory having a cell comprising an N.sup.+ type source region and drain region embedded in a P.sup.- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.

摘要翻译： 一种非易失性存储器，具有包含N +型源极区域和漏极区域的单元，该单元嵌入在P-型衬底中并被各个P口包围。 漏极和源极P型穴形成在两个不同的高角度硼注入步骤中，其设计用于优化植入能量和剂量，以确保电池的可扩展性并避免对回跳电压的损害。 所得到的电池与已知电池相比也具有更高的击穿电压。

公开(公告)号：US20130126822A1

公开(公告)日：2013-05-23

申请号：US13298962

申请日：2011-11-17

申请人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

发明人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

IPC分类号： H01L45/00 ,  H01L21/62

CPC分类号： H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

摘要： Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

摘要翻译： 一些实施例包括形成存储器单元的方法。 堆叠包括在导电区域上的超声波材料。 堆叠被图案化成沿着第一方向延伸的轨道。 轨道被图案化为支柱。 导电线形成在超声波材料上。 导电线沿着与第一方向相交的第二方向延伸。 导电线沿着第二方向互连柱。 一些实施例包括具有沿着第一方向延伸的第一导电线的存储器阵列。 这些线包含半导体材料的n型掺杂区域。 支柱超过第一导线，并且包含n型掺杂区域的台面以及p型掺杂区域和超声材料。 第二导电线在超声波材料之上并且沿与第一方向相交的第二方向延伸。 第二导电线沿着第二方向互连柱。

公开(公告)号：US6057591A

公开(公告)日：2000-05-02

申请号：US14437

申请日：1998-01-27

申请人： Camilla Calegari ,  Anna Carrara ,  Lorenzo Fratin ,  Carlo Riva

发明人： Camilla Calegari ,  Anna Carrara ,  Lorenzo Fratin ,  Carlo Riva

IPC分类号： H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L23/29

CPC分类号： H01L23/564 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/958

摘要： A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

摘要翻译： 一种用于形成器件边缘形态结构的方法，用于在半导体材料的衬底的主表面周围保护和密封电子电路。 电子电路是要求在至少一个电介质多层的主表面上形成的类型的电路。 电介质多层包括一层无定形平面化材料，其具有连续部分，该连续部分在形状结构中具有更内部的第一区域和更外部的第二区域的两个连续区域之间延伸。 设备边缘形态结构包括在基底中的形状结构的更内部的第一区域的主表面侧的开口，其中存在电介质多层的连续部分的区域。

公开(公告)号：US08154006B2

公开(公告)日：2012-04-10

申请号：US12345102

申请日：2008-12-29

申请人： Marcello Mariani ,  Lorenzo Fratin ,  Anna Rita Odorizzi ,  Michele Magistretti

发明人： Marcello Mariani ,  Lorenzo Fratin ,  Anna Rita Odorizzi ,  Michele Magistretti

IPC分类号： H01L45/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2445 ,  H01L45/06

摘要： A CMOS logic portion embedded with a PCM portion is recessed by a gate structure height as measured by a thickness of a gate oxide and a polysilicon gate to provide planarity of the CMOS logic portion with the PCM portion is described.

摘要翻译： 嵌入PCM部分的CMOS逻辑部分被栅极结构高度凹陷，栅极结构高度由栅极氧化物和多晶硅栅极的厚度测量，以提供CMOS逻辑部分与PCM部分的平面度。

公开(公告)号：US06369406B1

公开(公告)日：2002-04-09

申请号：US09311258

申请日：1999-05-13

申请人： Leonardo Ravazzi ,  Lorenzo Fratin

发明人： Leonardo Ravazzi ,  Lorenzo Fratin

IPC分类号： H01L2358

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for localizing point defects causing column leakage currents in a non-volatile memory device including a plurality of memory cells arranged in rows and columns in a matrix structure, source diffusions, and metal lines which connect said source diffusions to each other. Such a method includes the steps of: modifying the memory device in order to make source diffusions independent of each other and each one electrically connected to a respective row; sequentially biasing the single columns of the matrix; localizing the column to which at least one defective cell belongs, as soon as the leakage current flow occurs in the biased column; by keeping biased the localized column, biasing sequentially the single rows of the matrix to the same potential as that of the localized column; localizing a couple of cells, wherein at least one of them involves the point defects, as soon as the leakage current flow does not occur.

摘要翻译： 用于定位引起列漏电流的点缺陷的方法，所述非易失性存储器件包括以矩阵结构的行和列排列的多个存储单元，源扩散以及将所述源扩散相互连接的金属线。 这种方法包括以下步骤：修改存储器件以使源扩散彼此独立，每一个电连接到相应行; 顺序地偏置矩阵的单列; 一旦泄漏电流在偏置的列中发生，就定位至少一个有缺陷的单元所属的列; 通过保持偏置本地列，顺序地将矩阵的单行偏置到与局部列的相同的​​电位; 定位一对电池，其中一旦漏电流不发生，其中至少有一个电池涉及点缺陷。

公开(公告)号：US5977591A

公开(公告)日：1999-11-02

申请号：US824888

申请日：1997-03-18

申请人： Lorenzo Fratin ,  Carlo Riva

发明人： Lorenzo Fratin ,  Carlo Riva

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7836

摘要： A MOS transistor capable of withstanding relatively high voltages is of a type integrated on a region included in a substrate of semiconductor material, having conductivity of a first type and comprising a channel region intermediate between a first active region of source and a second active region of drain. Both these source and drain regions have conductivity of a second type and extend from a first surface of the substrate. The transistor also has a gate which includes at least a first polysilicon layer overlying the first surface of at least the channel region, to which it is coupled capacitively through a gate oxide layer. According to the invention, the first polysilicon layer includes a mid-portion which only overlies the channel region and has a first total conductivity of the first type, and a peripheral portion with a second total conductivity differentiated from the first total conductivity. The peripheral portion partly overlies the source and drain active regions toward the channel region.

摘要翻译： 能够承受相对高电压的MOS晶体管是集成在包括在半导体材料的衬底中的区域上的类型，其具有第一类型的导电性并且包括在源的第一有源区和第二有源区之间的沟道区 排水。 这些源极和漏极区都具有第二类型的导电性并且从衬底的第一表面延伸。 晶体管还具有栅极，该栅极至少包括覆盖至少沟道区的第一表面的第一多晶硅层，其通过栅极氧化物层电容耦合到该栅极氧化物层。 根据本发明，第一多晶硅层包括仅覆盖沟道区并具有第一类型的第一总电导率的中间部分，以及与第一总电导率不同的具有第二总电导率的外围部分。 外围部分部分地覆盖源极和漏极有源区域朝向沟道区域。

公开(公告)号：US5915185A

公开(公告)日：1999-06-22

申请号：US062859

申请日：1998-04-20

申请人： Lorenzo Fratin ,  Carlo Riva

发明人： Lorenzo Fratin ,  Carlo Riva

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/4238 ,  H01L21/26586 ,  H01L21/28123 ,  H01L29/0847

摘要： The method includes the following steps: delimiting active areas on a substrate, forming gate electrodes insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation to a reference line on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length, the widths of the gate electrode strips are determined at the design stage in relation to the orientation of the strips to the reference line and on the orientation of the directions of the implant beams.

摘要翻译： 该方法包括以下步骤：限定衬底上的有源区域，在有源区上形成与衬底绝缘的栅电极，并且用衬底的前表面进行多个注入步骤，以形成源区和漏区， 使用栅电极作为掩模。 注入束的方向由与前表面的倾斜角和通过前表面上的参考线的取向限定。 为了避免执行大量的植入步骤而没有前后通道的均匀和恒定的长度，栅极电极条的宽度在设计阶段相对于条与基准线的取向和植入物方向的取向相关来确定 梁。

公开(公告)号：US08546231B2

公开(公告)日：2013-10-01

申请号：US13298962

申请日：2011-11-17

申请人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

发明人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

IPC分类号： G11C17/16

CPC分类号： H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

摘要： Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

公开(公告)号：US06507067B1

公开(公告)日：2003-01-14

申请号：US08692936

申请日：1996-07-31

申请人： Lorenzo Fratin ,  Leonardo Ravazzi ,  Carlo Riva

发明人： Lorenzo Fratin ,  Leonardo Ravazzi ,  Carlo Riva

IPC分类号： H01L29788

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.

摘要翻译： 一种具有存储单元阵列的闪存EEPROM，其包括连接存储单元的源电极的公共源极线。 当存储器单元必须被电擦除时，电阻反馈元件串联耦合在公共源极线和正电位之间。 闪存EEPROM包括耦合到公共源极线的电压限制电路，用于将公共源极线的电位限制为比正电位低的规定最大值。

公开(公告)号：US06462400B1

公开(公告)日：2002-10-08

申请号：US09483656

申请日：2000-01-14

申请人： Federico Pio ,  Paola Zuliani ,  Lorenzo Fratin

发明人： Federico Pio ,  Paola Zuliani ,  Lorenzo Fratin

IPC分类号： H01L23544

CPC分类号： H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Chip Outline Band (COB) structure for an integrated circuit integrated in a semiconductor chip having a semiconductor substrate of a first conductivity type and biased at a common reference potential of the integrated circuit, the COB structure comprising a substantially annular region formed in the substrate along a periphery thereof, and at least one annular conductor region superimposed on and contacting the substantially annular region, wherein the substantially annular region is electrically connected at the common reference potential.

摘要翻译： 用于集成在具有第一导电类型的半导体衬底并被偏置在集成电路的公共参考电位的半导体芯片中的集成电路的芯片外形带（COB）结构，所述COB结构包括形成在衬底中的大致环形区域 其外围，以及叠加在基本环形区域上并接触大致环形区域的至少一个环形导体区域，其中大致环形区域以公共参考电位电连接。