公开(公告)号：US06831325B2

公开(公告)日：2004-12-14

申请号：US10327336

申请日：2002-12-20

申请人： Bohumil Lojek

发明人： Bohumil Lojek

IPC分类号： H01L29788

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7887

摘要： A multi-level non-volatile memory transistor is formed in a semiconductor substrate. A conductive polysilicon control gate having opposed sidewalls is insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. Auxillary low voltage transistors which may be made at the same time as the formation of the memory transistor apply opposite phase clock pulses to source and drain electrodes so that first one side of the memory transistor may be written to, or read, then the other side.

摘要翻译： 在半导体衬底中形成多级非易失性存储晶体管。 具有相对侧壁的导电多晶硅控制栅极绝对地间隔在衬底上方。 导电多晶硅间隔物通过薄的隧道氧化物与相对的侧壁分离。 源极和漏极植入物在间隔物的下方或稍微外侧。 绝缘材料放置在结构上方，在控制栅极上方有一个孔，用于与连接到导电字线或部分导电字线的栅电极接触。 可以在形成存储晶体管的同时进行的辅助低压晶体管对源电极和漏电极施加相反的相位时钟脉冲，使得存储晶体管的第一个一侧可以被写入或读取，然后是另一侧 。

公开(公告)号：US06818943B2

公开(公告)日：2004-11-16

申请号：US10269951

申请日：2002-10-15

申请人： Yoshihiro Kumazaki

发明人： Yoshihiro Kumazaki

IPC分类号： H01L29788

CPC分类号： H01L27/11502 ,  H01L27/105 ,  H01L27/1203 ,  H01L29/7883

摘要： A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film. This invention can realize a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error by minimizing variations in the threshold value.

摘要翻译： 本发明的半导体器件是在半导体衬底上形成具有预定形状的浮动栅极的单层栅极非易失性半导体存储器。 该浮置栅极通过栅极氧化膜与扩散层对置，并通过使用栅极氧化膜作为电介质膜与扩散层电容耦合。 电介质膜正下方的扩散层通过绝缘膜例如氧化硅膜与半导体基板绝缘。 在隧道氧化膜上延伸的浮置栅极的两侧的半导体衬底的表面区域中形成一对扩散层。 本发明可以实现可靠的半导体器件，其是可以进行低成本处理的单层栅极半导体器件，具有可以很好地承受当数据被擦除或写入时施加的高电压的控制栅极，并且可以防止 最小化阈值变化的操作误差。

公开(公告)号：US06812517B2

公开(公告)日：2004-11-02

申请号：US10230810

申请日：2002-08-29

申请人： Frank Kelsey Baker

发明人： Frank Kelsey Baker

IPC分类号： H01L29788

CPC分类号： H01L29/66833 ,  H01L27/11568 ,  H01L29/792

摘要： A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.

公开(公告)号：US06812515B2

公开(公告)日：2004-11-02

申请号：US09994545

申请日：2001-11-26

申请人： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

发明人： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

IPC分类号： H01L29788

CPC分类号： H01L29/4916 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

摘要： A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.

摘要翻译： 非易失性存储单元包括在衬底区域上的第一绝缘层和浮置栅极。 浮置栅极包括在第一绝缘层之上的第一多晶硅层和在第一多晶硅层上并与第一多晶硅层接触的第二多晶硅层。 第一多晶硅层具有预定的掺杂浓度，并且第二多晶硅层具有在远离第一和第二多晶硅层之间的界面的方向上减小的掺杂浓度。 第二绝缘层覆盖并与第二多晶硅层接触。 控制栅极包括在第二绝缘层上并与第二绝缘层接触的第三多晶硅层，以及在第三多晶硅层上并与第三多晶硅层接触的第四多晶硅层。 第四多晶硅层具有预定的掺杂浓度，并且第三多晶硅层具有在远离第三和第四多晶硅层之间的界面的方向上减小的掺杂浓度。

公开(公告)号：US06781189B2

公开(公告)日：2004-08-24

申请号：US10056179

申请日：2002-01-22

申请人： Theodore M. Taylor

发明人： Theodore M. Taylor

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7881

摘要： Embodiments in accordance with the present invention provide for forming floating gate transistor structures as well as the structures so formed. An exemplary method provides a substrate encompassing semiconductive material. A first layer is formed over the semiconductive material. At least one pair of spaced shallow trench isolation (STI) structures are formed extending through the first layer and into the semiconductive material, and at least a portion of the first layer between the spaced STI structures is removed effective to form a recess there between. The recess is at least partially filled by forming a conductive floating gate material therein and a control gate is formed operatively over the conductive floating gate material to form the floating gate transistor.

摘要翻译： 根据本发明的实施例提供了形成浮栅晶体管结构以及如此形成的结构。 示例性方法提供了包含半导体材料的基底。 在半导体材料上形成第一层。 形成至少一对隔开的浅沟槽隔离（STI）结构，延伸穿过第一层并进入半导体材料，并且有效地在间隔开的STI结构之间的第一层的至少一部分被去除以在其间形成凹部。 通过在其中形成导电浮栅材料至少部分地填充凹槽，并且在导电浮栅材料上可操作地形成控制栅极以形成浮栅晶体管。

公开(公告)号：US06774431B2

公开(公告)日：2004-08-10

申请号：US10374289

申请日：2003-02-25

申请人： Paul Rudeck

发明人： Paul Rudeck

IPC分类号： H01L29788

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A floating gate transistor includes a first floating gate portion extending horizontally over a channel region. A second floating gate portion vertically extends upwardly from the first floating gate portion to be coupled to a control gate. The second floating gate portion can be formed in a container shape with the control gate formed within the container floating gate. The transistor allows the die real estate occupied by the transistor to be reduced while maintaining the coupling area between the floating and control gates. The transistor can be used in non-volatile memory devices, such as flash memory.

摘要翻译： 浮栅晶体管包括在沟道区域上水平延伸的第一浮栅部分。 第二浮栅部分从第一浮动栅极部分垂直向上延伸以耦合到控制栅极。 第二浮栅部分可以形成为容器形状，其中控制栅极形成在容器浮动栅极内。 晶体管允许在保持浮置和控制栅极之间的耦合区域的同时减小由晶体管占据的裸片空间。 晶体管可用于非易失性存储器件，如闪存。

公开(公告)号：US06768160B1

公开(公告)日：2004-07-27

申请号：US10352658

申请日：2003-01-28

申请人： Yu Li ,  Zhizheng Liu ,  Mark W. Randolph

发明人： Yu Li ,  Zhizheng Liu ,  Mark W. Randolph

IPC分类号： H01L29788

CPC分类号： H01L29/78696 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7885 ,  H01L29/792

摘要： An array of non-volatile memory cells is provided for storing a data pattern and reproducing the data pattern. The array comprises a semiconductor substrate moderately doped with a first type of impurity to enhance conductivity. A plurality of bit lines within the substrate define a plurality of vertical channel regions spaced there between. Each bit line comprises the substrate doped with a second type of impurity to enhance conductivity. Each channel comprises a moderately doped channel region portion adjacent to a first one of the bit lines and a slightly more heavily doped channel region portion adjacent to a second one of the bit lines. A plurality of parallel spaced apart semiconductor word lines are positioned over the substrate and separated from the substrate by an insulator film, a charge storage region, and a second insulator film. An array control circuit is coupled to each bit line and each word line to provide a drain bit line programming potential the second one of the bit line diffusions to accelerating electrons from the first one of the bit line diffusions towards the second one of the bit line diffusions and to provide a word line programming potential to a selected one of the word lines to divert the accelerated electrons from the channel region beneath the selected word line across the insulator film into the charge storage region.

摘要翻译： 提供了一组非易失性存储器单元，用于存储数据模式并再现数据模式。 该阵列包括适度地掺杂有第一类杂质以增强导电性的半导体衬底。 衬底内的多个位线限定了在其之间间隔开的多个垂直沟道区域。 每个位线包括掺杂有第二类杂质的衬底以增强导电性。 每个通道包括与第一位线相邻的适度掺杂的沟道区域部分和与第二位线相邻的稍高掺杂的沟道区域部分。 多个并联的间隔开的半导体字线位于衬底之上并且通过绝缘膜，电荷存储区和第二绝缘膜与衬底分离。 阵列控制电路耦合到每个位线和每个字线，以提供漏极位线编程电位，位线扩散中的第二个位加速电子从位线扩散中的第一个朝向位线的第二个 并且为所选择的一条字线提供字线编程电位，以将加速电子从所选择的字线下方的沟道区域跨过绝缘膜转移到电荷存储区域中。

公开(公告)号：US06765260B1

公开(公告)日：2004-07-20

申请号：US10249024

申请日：2003-03-11

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A flash memory with a self-aligned spilt gate and the methods for fabricating and operating the same are described. The flash cell consists of a substrate having a deep n-type well and a shallow p-type well in the deep n-type well therein, a control gate structure on the gate oxide layer located on the p-type shallow well, a floating gate on one sidewall of the control gate and over the substrate, a tunnel oxide layer between the control gate and the floating gate and between the floating gate and the substrate, a drain and a common source disposed beneath each side of the control gate in the substrate, wherein the depth of the drain and the common source are larger than the depth of the shallow p-type well, a pocket p-type well in the substrate around the drain and electrically connecting with the shallow p-type well.

摘要翻译： 描述了具有自对准溢流门的闪速存储器及其制造和操作方法。 闪存单元由深n型阱中的深n型阱和浅p型阱构成的衬底，位于p型浅阱上的栅极氧化物层上的控制栅极结构，浮置 栅极在控制栅极的一个侧壁上并且在衬底上方，在控制栅极和浮置栅极之间以及浮置栅极和衬底之间的隧道氧化物层，漏极和设置在控制栅极的每一侧下方的公共源 衬底，其中漏极和公共源的深度大于浅p型阱的深度，在漏极周围的衬底中的凹坑p型阱，并与浅的p型阱电连接。

公开(公告)号：US06759708B2

公开(公告)日：2004-07-06

申请号：US10273053

申请日：2002-10-17

申请人： Kelly T. Hurley ,  Graham Wolstenholme

发明人： Kelly T. Hurley ,  Graham Wolstenholme

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

摘要翻译： 公开了根据本发明的在堆叠栅极区域中的至少一个多晶硅结构的半导体器件。 堆叠栅极区域包括衬底，至少一个沟槽，氧化物层，至少一个浮置栅极层和至少一个多晶硅结构。 所述至少一个多晶硅结构形成为与所述至少一个浮动栅极层的垂直边缘相邻并且在所述氧化物层上方形成。 多晶硅结构，其包括多晶硅翼和耳，用于增加存储器件中存储器单元的电容耦合，从而允许进一步减小或缩小存储器单元和器件的尺寸。

公开(公告)号：US06759695B2

公开(公告)日：2004-07-06

申请号：US10661429

申请日：2003-09-11

申请人： Yanjun Ma ,  Douglas James Tweet ,  David Russell Evans

发明人： Yanjun Ma ,  Douglas James Tweet ,  David Russell Evans

IPC分类号： H01L29788

CPC分类号： H01L29/66916 ,  H01L29/802

摘要： An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

摘要翻译： 集成电路金属氧化物半导体器件包括位于其中的栅极区域和电介质层，其中介电层基本上不含有从器件的硅锗层扩散的锗。 该方法包括沉积虚拟置换栅极，对器件进行高温处理，去除伪栅极，然后在所形成的栅极区域内沉积介电材料和最终栅极材料。 因为在器件的高温处理之后沉积介电材料，所以锗可以扩散到电介质材料中。