A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response to reception timing of the command signal. Since the command signal can be received in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when a reception rate is the same as that of the conventional art. As a result of this, in a system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce power consumption of a clock synchronization circuit in the system, without reducing a data input/output rate for the semiconductor memory device.