公开(公告)号：US08553459B2

公开(公告)日：2013-10-08

申请号：US13081094

申请日：2011-04-06

Applicant: Naoharu Shinozaki ,  Masao Taguchi ,  Takahiro Hatada ,  Satoru Sugimoto ,  Satoshi Sakurakawa

Inventor： Naoharu Shinozaki ,  Masao Taguchi ,  Takahiro Hatada ,  Satoru Sugimoto ,  Satoshi Sakurakawa

IPC: G11C11/34

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/22

Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.

Abstract translation: 非易失性半导体存储器件包括：第一串，包括串联连接的第一数量的存储单元，以非易失性方式存储信息; 并且包括串联连接的第二数量的存储单元的第二串，其以非易失性方式存储信息，其中第二数小于第一数量。

公开(公告)号：US20120319912A1

公开(公告)日：2012-12-20

申请号：US13494713

申请日：2012-06-12

Applicant: Masao TAGUCHI

Inventor： Masao TAGUCHI

IPC: H01Q21/00 ,  H01Q7/06 ,  H01Q7/00

CPC classification number: G06K19/07345

Abstract: A device includes a first substrate that has a first antenna having a first loop and second loop that form loop shapes viewed in a planar projection; and a second substrate that has a second antenna having a third loop and fourth loop that form loop shapes viewed in the planar projection. The first substrate and the second substrate are disposed so that the first antenna and the second antenna face each other. At least when the first substrate and the second substrate operate, the first antenna and the second antenna are in a state that the first antenna and the second antenna are capable of being magnetically coupled.

Abstract translation: 一种器件包括第一衬底，其具有第一天线，其具有第一环和第二环，所述第一环形成在平面突起中形成的环形形状; 以及具有第二天线的第二基板，所述第二天线具有形成在所述平面投影中观察的环形的第三环和第四环。 第一基板和第二基板被配置为使得第一天线和第二天线彼此面对。 至少当第一基板和第二基板工作时，第一天线和第二天线处于第一天线和第二天线能够被磁耦合的状态。

公开(公告)号：US20120051115A1

公开(公告)日：2012-03-01

申请号：US13289553

申请日：2011-11-04

Applicant: Masao Taguchi

Inventor： Masao Taguchi

IPC: G11C11/00

CPC classification number: G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/78 ,  G11C2213/79

Abstract: A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.

Abstract translation: 电阻改变存储器阵列架构包括排列成行和列的电阻改变存储单元单元的阵列，其中至少两个相邻列共享一个感测位线，以及一个单独与每列相关联的控制线，其中每个中的电流控制部件 沿着相应列的单位单元耦合到相应的控制线。 该架构进一步包括多个与相应行相关联的字线，其中与相应行的每个单位单元相关联的电阻改变元件被耦合到相应的字线。

公开(公告)号：US20110261622A1

公开(公告)日：2011-10-27

申请号：US13081094

申请日：2011-04-06

Applicant: Naoharu Shinozaki ,  Masao Taguchi ,  Takahiro Hatada ,  Satoru Sugimoto ,  Satoshi Sakurakawa

Inventor： Naoharu Shinozaki ,  Masao Taguchi ,  Takahiro Hatada ,  Satoru Sugimoto ,  Satoshi Sakurakawa

IPC: G11C16/08

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/22

Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.

Abstract translation: 非易失性半导体存储器件包括：第一串，包括串联连接的第一数量的存储单元，以非易失性方式存储信息; 并且包括串联连接的第二数量的存储单元的第二串，其以非易失性方式存储信息，其中第二数小于第一数量。

公开(公告)号：US07462539B2

公开(公告)日：2008-12-09

申请号：US11892872

申请日：2007-08-28

Applicant: Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

Inventor： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

IPC: H01L21/00 ,  H01L21/20

CPC classification number: H01L27/11526 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/0692 ,  H01L29/7883

Abstract: A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select transistor region; a tunnel insulating film formed on a partial area of the direct tunnel element region and having a thickness different from a thickness of the gate insulating film; a continuous floating gate electrode formed above the gate insulating film and the tunnel insulating film; an inter-electrode insulating film formed on a surface of the floating gate electrode; a control gate electrode facing the floating gate electrode via the inter-electrode insulating film; and a pair of source/drain regions formed on both sides of the channel region of the select transistor region and not overlapping the tunnel insulating film.

Abstract translation: 半导体器件具有形成在半导体衬底上的隔离区域，并且限定包括选择晶体管区域和直接隧道元件区域的连续有源区域; 形成在所述选择晶体管区域的沟道区上的栅极绝缘膜; 隧道绝缘膜，其形成在所述直接隧道元件区域的部分区域上，并且具有与所述栅极绝缘膜的厚度不同的厚度; 形成在栅极绝缘膜和隧道绝缘膜上方的连续浮栅; 形成在所述浮栅电极的表面上的电极间绝缘膜; 通过所述电极间绝缘膜与所述浮栅相对的控制栅电极; 以及形成在选择晶体管区域的沟道区域的两侧并且不与隧道绝缘膜重叠的一对源极/漏极区域。

公开(公告)号：US06744300B2

公开(公告)日：2004-06-01

申请号：US10277707

申请日：2002-10-23

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC: H01J1982

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract translation: 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US06498524B1

公开(公告)日：2002-12-24

申请号：US09706731

申请日：2000-11-07

Applicant: Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

Inventor： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC: H03L708

CPC classification number: G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

Abstract translation: 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06492846B1

公开(公告)日：2002-12-10

申请号：US09474702

申请日：1999-12-29

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC: H03K300

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By this constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract translation: 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过这种结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US06480030B1

公开(公告)日：2002-11-12

申请号：US09648621

申请日：2000-08-28

Applicant: Masao Taguchi

Inventor： Masao Taguchi

IPC: H03K190175

CPC classification number: G11C7/1057 ,  G06F13/4077 ,  G06F13/4086 ,  G11C7/1051 ,  G11C2207/2227 ,  H03K19/0016 ,  H03K19/017545 ,  H03K19/018585 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.

Abstract translation: 用于信号传输的系统具有用于信号传输的至少一个总线和设置在连接到总线的短截线上的防反射电阻，用于防止在总线和短截线之间的交叉点处的信号的反射。 该系统包括终端电阻以及用于通过第一模式中的终端电阻将总线耦合到终端电压并且用于在第二模式中将总线与终端电压断开的开关单元。

公开(公告)号：US06298004B1

公开(公告)日：2001-10-02

申请号：US08892790

申请日：1997-07-15

Applicant: Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

Inventor： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC: G11C800

CPC classification number: G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

Abstract translation: 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。