A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.