公开(公告)号：US06784723B2

公开(公告)日：2004-08-31

申请号：US09896133

申请日：2001-06-29

申请人： Sang-Kwon Lee ,  Joon-Ho Kim ,  Young-Jun Nam ,  Kwang-Rae Cho ,  Byung-Jae Lee

发明人： Sang-Kwon Lee ,  Joon-Ho Kim ,  Young-Jun Nam ,  Kwang-Rae Cho ,  Byung-Jae Lee

IPC分类号： G05F302

CPC分类号： H02M3/073 ,  H02M2003/077

摘要： The present invention is a high-voltage generation circuit configured to sequentially activate a plurality of high-voltage pump circuits to precisely pump a level of high voltage. In one embodiment, the high-voltage generation circuit includes a high-voltage level detection unit for outputting a high-voltage detected signal, a high-voltage pump control unit for generating a control signal responsive to a detected signal, an oscillator for generating a pulse signal for driving a plurality of high-voltage pumps, a sequential delay unit for sequentially delaying the pulse signal from the oscillator, and a plurality of high-voltage pumps for pumping the high voltage based on a delayed pulse signal and the control signal.

摘要翻译： 本发明是一种高电压发生电路，其被配置为顺序启动多个高压泵电路以精确地泵浦高电压。 在一个实施例中，高电压发生电路包括用于输出高电压检测信号的高电压电平检测单元，用于响应于检测到的信号产生控制信号的高压泵控制单元，用于产生 用于驱动多个高压泵的脉冲信号，用于顺序地延迟来自振荡器的脉冲信号的顺序延迟单元，以及用于基于延迟的脉冲信号和控制信号来泵送高电压的多个高压泵。

公开(公告)号：US20050067423A1

公开(公告)日：2005-03-31

申请号：US10690896

申请日：2003-10-22

申请人： Kwang-Rae Cho

发明人： Kwang-Rae Cho

IPC分类号： A47K7/00 ,  A45D40/00 ,  A47K10/16 ,  A47K10/20 ,  A61F13/84 ,  A61F15/00 ,  B65D75/34 ,  B65D77/08 ,  B65D81/32 ,  B65D83/00 ,  B65H1/00 ,  D21H27/30 ,  D21H27/38

CPC分类号： A45D40/0087 ,  A45D2200/1027 ,  A45D2200/1036 ,  A45D2200/1045 ,  A61F15/00

摘要： The present invention relates to a disposable tissue structure which includes an upper unit having a plurality of compressed tissue storing units, each compressed tissue storing unit having a lower opened side and an upper closed side and being hollow and upwardly protruded from an upper surface of the upper unit for storing a compressed tissue therein which is compressed using a non-woven fabric, pulp or the like and is formed in a certain shape, so that the compressed tissue is changed to a disposable wet tissue when a certain liquid is absorbed to the compressed tissue, a middle unit which is sealingly adhered to a lower surface of the upper unit and has a certain thickness and tearing strength, the middle unit being forked in a flat plate shape, and a lower unit which is sealingly adhered to a lower surface of the middle unit and has a plurality of liquid storing units which are formed in the same construction as the inverted upper unit, the liquid storing unit having an opened upper side and closed lower side and being hollow and downwardly protruded from a lower surface of the lower unit for thereby storing a liquid having a certain function.

摘要翻译： 本发明涉及一次性组织结构，其包括具有多个压缩组织储存单元的上部单元，每个压缩的组织储存单元具有下开口侧和上封闭侧，并且是中空的并且从上表面向上突出 上部单元，用于存储使用无纺布，纸浆等压缩的压缩的组织，并且形成为一定形状，使得当某些液体被吸收到所述压缩组织时，被压缩的组织变为一次性湿纸巾 压缩组织，密封地粘附到上部单元的下表面并具有一定厚度和撕裂强度的中间单元，中间单元被分叉成平板形状，下部单元密封地粘附到下表面 并具有与倒置的上部单元相同的结构形成的多个液体存储单元，液体存储单元具有打开的上部 并且从下部单元的下表面向下突出，从而存储具有一定功能的液体。

公开(公告)号：US07034598B2

公开(公告)日：2006-04-25

申请号：US10335013

申请日：2002-12-31

申请人： Kwang-Rae Cho

发明人： Kwang-Rae Cho

IPC分类号： H03H11/26

CPC分类号： G01R31/2621

摘要： A switching point detection circuit for detecting a switching point according to a fabrication condition of a MOS transistor includes a reference voltage generation circuit for generating a reference voltage, a first CMOS inverter circuit for receiving the reference voltage, and a second CMOS inverter circuit for receiving the reference voltage, wherein an NMOS transistor is a dominant transistor for the reference voltage in the first CMOS inverter circuit and a PMOS transistor is a dominant transistor for the reference voltage in the second CMOS inverter circuit.

摘要翻译： 根据MOS晶体管的制造条件检测开关点的开关点检测电路包括：用于产生参考电压的基准电压产生电路，用于接收参考电压的第一CMOS反相器电路和用于接收参考电压的第二CMOS反相器电路 参考电压，其中NMOS晶体管是用于第一CMOS反相器电路中的参考电压的主要晶体管，并且PMOS晶体管是第二CMOS反相器电路中用于参考电压的主要晶体管。

公开(公告)号：US06333886B2

公开(公告)日：2001-12-25

申请号：US09745427

申请日：2000-12-26

申请人： Kwang-Rae Cho ,  Joon-Ho Kim

发明人： Kwang-Rae Cho ,  Joon-Ho Kim

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C11/406 ,  G11C11/4076

摘要： A self refresh controlling apparatus for use in a semiconductor memory device includes a delay unit for delaying the clock buffer enable control signal by a predetermined time and an internal clock signal activation controller for controlling activation of the internal clock signal by logically combining the internal clock signal with a control signal generated under control of the delayed clock buffer enable control signal from the delaying unit and the internal clock signal in order to prevent mis-operation due to the internal clock signal generated late in completion of self refresh operation.

公开(公告)号：US06870416B2

公开(公告)日：2005-03-22

申请号：US10617180

申请日：2003-07-11

申请人： Kwang-Rae Cho

发明人： Kwang-Rae Cho

IPC分类号： G11C11/40 ,  G06F1/10 ,  H03K5/24 ,  H03K3/00

CPC分类号： H03K5/2481 ,  G06F1/10

摘要： A semiconductor device includes a clock buffer block for receiving and buffering an external clock signal and then outputting an internal clock in response is a second control signal; a clock enable buffer block, which is enabled by a buffer enable signal, for comparing a reference voltage having a constant potential with a clock enable buffer signal and then generating a first control signal; a clock enable signal timing control block for outputting the second control signal by passing the clock enable signal to the clock buffer block in response to the buffer enable signal or by delaying the clock enable signal for a predetermined time; and a clock enable signal latch block for generating the enable signal after a power-up signal is inputted.

摘要翻译： 半导体器件包括用于接收和缓冲外部时钟信号的时钟缓冲器块，然后响应地输出内部时钟是第二控制信号; 时钟使能缓冲块，其由缓冲器使能信号使能，用于将具有恒定电位的参考电压与时钟使能缓冲器信号进行比较，然后产生第一控制信号; 时钟使能信号定时控制块，用于通过响应于缓冲器使能信号将时钟使能信号传递到时钟缓冲器块，或通过将时钟使能信号延迟预定时间来输出第二控制信号; 以及用于在输入上电信号之后产生使能信号的时钟使能信号锁存块。

公开(公告)号：US06545938B2

公开(公告)日：2003-04-08

申请号：US09886465

申请日：2001-06-22

申请人： Byung Jae Lee ,  Joon Ho Kim ,  Young Jun Nam ,  Kwang Rae Cho ,  Sang Kwon Lee

发明人： Byung Jae Lee ,  Joon Ho Kim ,  Young Jun Nam ,  Kwang Rae Cho ,  Sang Kwon Lee

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4082 ,  G11C2207/2227

摘要： A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.