发明授权
US06549028B1 Configuration and process for testing a multiplicity of semiconductor chips on a wafer plane
有权
用于在晶圆平面上测试多个半导体芯片的配置和处理
- 专利标题： Configuration and process for testing a multiplicity of semiconductor chips on a wafer plane
- 专利标题（中）： 用于在晶圆平面上测试多个半导体芯片的配置和处理
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申请号： US09630972申请日： 2000-08-02
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公开(公告)号： US06549028B1公开(公告)日： 2003-04-15
- 发明人: Carsten Ohlhoff
- 申请人： Carsten Ohlhoff
- 优先权： DE19936321 19990802
- 主分类号： G01R3128
- IPC分类号： G01R3128
摘要：
Arrangement and method for testing a multiplicity of semiconductor chips at the wafer level The invention relates to an arrangement and a method for testing a multiplicity of semiconductor chips (7) at the wafer level, in which an intermediate wiring plane (10) with a global test bus (12) and test pads (11) is applied to the surface of the wafer (6).