发明授权
- 专利标题: Timing optimization in presence of interconnect delays
- 专利标题(中): 存在互连延迟的定时优化
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申请号: US09300557申请日: 1999-04-27
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公开(公告)号: US06553338B1公开(公告)日: 2003-04-22
- 发明人: Premal V. Buch , Hamid Savoj , Lukas P. P. P. Van Ginneken
- 申请人: Premal V. Buch , Hamid Savoj , Lukas P. P. P. Van Ginneken
- 主分类号: G06F1750
- IPC分类号: G06F1750
摘要:
A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.
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