发明授权
US06553338B1 Timing optimization in presence of interconnect delays 有权
存在互连延迟的定时优化

Timing optimization in presence of interconnect delays
摘要:
A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.
信息查询
0/0