公开(公告)号：US06553338B1

公开(公告)日：2003-04-22

申请号：US09300557

申请日：1999-04-27

申请人： Premal V. Buch ,  Hamid Savoj ,  Lukas P. P. P. Van Ginneken

发明人： Premal V. Buch ,  Hamid Savoj ,  Lukas P. P. P. Van Ginneken

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F17/5022

摘要： A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.

摘要翻译： 提出了在任意数量的等间距单个缓冲器中缓冲的无限长的线的情况下的优化缓冲策略。 提出了一种简单而有效的技术，用于选择缓冲区大小，并确定前面的良好的缓冲间距离，从而实现快速，高效的缓冲区插入。 该分析还允许将长线的延迟表示为长度和缓冲器和线宽的简单函数。 基于此，提出了一种新颖的恒定线延迟方法，其中提出的线延迟模型用于在设计过程的早期对线延迟进行相当准确的预测，并且这些预测稍后通过缓冲器插入和线尺寸来满足。

公开(公告)号：US06931610B1

公开(公告)日：2005-08-16

申请号：US09570081

申请日：2000-05-12

申请人： Premal V. Buch ,  Manjit Borah

发明人： Premal V. Buch ,  Manjit Borah

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A fast method of estimating capacitances and wire delays in an integrated circuit design is based on placement information such as that contained in a gate schematic net list from a logic synthesis tool. A simple tree topology called a spine tree is constructed to connect the pins of the net as an approximation of actual connections therein. Capacitance is extracted for this topology assuming a worst case scenario, and Elmore delays are computed for the wire delays based on the worst-case capacitances. The method takes linear time as a function of the number of pins in the net and is much faster than using a Steiner tree method in this context.

摘要翻译： 在集成电路设计中估计电容和导线延迟的快速方法基于诸如包含在来自逻辑综合工具的门逻辑网络列表中的放置信息。 被称为脊柱树的简单树状拓扑被构造成连接网的引脚作为其中的实际连接的近似值。 假设最坏情况下，为此拓扑提取电容，并根据最坏情况下的电容计算导线延迟的Elmore延迟。 该方法将线性时间作为网络中的引脚数量的函数，并且比在本上下文中使用Steiner树方法要快得多。