发明授权
- 专利标题: Method of producing a semiconductor memory device using a self-alignment process
- 专利标题(中): 使用自对准方法制造半导体存储器件的方法
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申请号: US09826088申请日: 2001-04-05
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公开(公告)号: US06576510B2公开(公告)日: 2003-06-10
- 发明人: Toshiaki Yamanaka , Shin' ichiro Kimura , Hideyuki Matsuoka , Tomonori Sekiguchi , Takeshi Sakata , Kiyoo Itoh
- 申请人: Toshiaki Yamanaka , Shin' ichiro Kimura , Hideyuki Matsuoka , Tomonori Sekiguchi , Takeshi Sakata , Kiyoo Itoh
- 主分类号: H01L218242
- IPC分类号: H01L218242
摘要:
According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.
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