利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

179 条记录 (耗时 0.033 秒)

    Semiconductor memory device and manufacturing method thereof
    5.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US06791134B2

    公开(公告)日：2004-09-14

    申请号：US10205421

    申请日：2002-07-26

    申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

    发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

    IPC分类号： H01L27108

    CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

    摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

    摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小， 随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触 （33），外围电路区域和存储单元区域之间的台阶高度显着降低。

    Semiconductor storage device and process for manufacturing the same
    7.
    发明授权
    Semiconductor storage device and process for manufacturing the same 失效
    半导体存储装置及其制造方法

    公开(公告)号：US06617205B1

    公开(公告)日：2003-09-09

    申请号：US09077100

    申请日：1998-05-20

    申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

    发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

    摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

    摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小， 随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触 （33），外围电路区域和存储单元区域之间的台阶高度显着降低。

    Semiconductor memory device and method of manufacturing the same
    9.
    发明授权
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US06831316B1

    公开(公告)日：2004-12-14

    申请号：US10009826

    申请日：2002-03-19

    申请人： Hideyuki Matsuoka ,  Takeshi Sakata ,  Shinichiro Kimura ,  Toshiaki Yamanaka ,  Tsuyoshi Kachi ,  Tomonori Sekiguchi

    发明人： Hideyuki Matsuoka ,  Takeshi Sakata ,  Shinichiro Kimura ,  Toshiaki Yamanaka ,  Tsuyoshi Kachi ,  Tomonori Sekiguchi

    IPC分类号： H01L4700

    CPC分类号： H01L27/108 ,  H01L27/10894 ,  H01L27/10897

    摘要： An existent DRAM memory cell comprises transistors as a switch and capacitors for accumulating storage charges in which the height of the capacitor has been increased more and more along with micro miniaturization, which directly leads to increase in the manufacturing cost. The invention of the present application provides a semiconductor memory device of a basic constitution in which a memory cell array having plural memory cells disposed on a semiconductor substrate and word lines and data lines for selecting the memory cells and a peripheral circuit at the periphery of the memory cell array wherein the memory cell comprises a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and a potential can be applied to the insulating layer enabling the tunneling effect. The invention of the present application concerns a memory cell not requiring capacitor and capable of being formed in simple steps.

    摘要翻译： 存在的DRAM存储单元包括作为开关的晶体管和用于累积存储电荷的电容器，其中电容器的高度随着微型化而逐渐增加，这直接导致制造成本的增加。 本申请的发明提供了一种基本结构的半导体存储器件，其中具有设置在半导体衬底上的多个存储单元的存储单元阵列和用于选择存储单元的字线和数据线以及外围电路的外围电路 存储单元阵列，其中存储单元包括导电层的多层，绝缘层和含有杂质的多个半导体层，并且可以将电位施加到能够实现隧道效应的绝缘层。 本申请的发明涉及不需要电容器并能够以简单的步骤形成的存储单元。

    Semiconductor integrated circuit device
    10.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06207986B1

    公开(公告)日：2001-03-27

    申请号：US09383367

    申请日：1999-08-26

    申请人： Toshiaki Yamanaka ,  Shin'ichiro Kimura ,  Hideyuki Matsuoka ,  Takeshi Sakata ,  Tomonori Sekiguchi

    发明人： Toshiaki Yamanaka ,  Shin'ichiro Kimura ,  Hideyuki Matsuoka ,  Takeshi Sakata ,  Tomonori Sekiguchi

    IPC分类号： H01L2710

    CPC分类号： H01L23/528 ,  H01L27/10894 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device offering a phase pattern makeup that excludes mixture of insular and linear patterns in a mask for forming a single wire electrode layer so as to eliminate inconsistency in the Levenson arrangement of phase shifters. A plurality of wire electrodes are spaced a minimum size apart and are in different phases. Between two adjacent wire electrodes are plug electrodes each formed with an upper and a lower layer plug electrode in direct contact, with no intervention of wire electrodes and without the presence of an insular pattern made of the same wire electrode layer. This setup allows the Levenson arrangement to take shape for enhanced pattern density, whereby a semiconductor integrated circuit device of a high degree of integration is implemented.

    摘要翻译： 一种提供相位图案化妆的半导体集成电路器件，其排除了用于形成单线电极层的掩模中的孤岛和线性图案的混合，以消除移相器的列文森布置中的不一致。 多个线电极间隔开最小尺寸并处于不同的相位。 在两个相邻的线电极之间是每个形成有直接接触的上层和下层电极电极的插头电极，没有线电极的介入，并且不存在由相同的线电极层制成的岛状图案。 该设置允许莱文森布置形成增强的图案密度，从而实现高集成度的半导体集成电路器件。