公开(公告)号：US07667259B2

公开(公告)日：2010-02-23

申请号：US11452256

申请日：2006-06-14

申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC分类号： H01L21/00

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

摘要翻译： 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而产生的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

公开(公告)号：USRE38296E1

公开(公告)日：2003-11-04

申请号：US08408788

申请日：1995-03-23

申请人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

发明人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

IPC分类号： H01L27108

CPC分类号： H01L27/10808 ,  H01L27/105 ,  H01L27/10852

摘要： A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.

公开(公告)号：US5196910A

公开(公告)日：1993-03-23

申请号：US650999

申请日：1991-02-04

申请人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

发明人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/105

摘要： A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.

摘要翻译： 一种半导体存储器，其中具有多个存储单元的存储单元区域和半导体衬底的表面上方相对高的高度形成在具有凹部和突出部分的半导体衬底的凹部中，并且其中外围电路区域 在半导体衬底的突出部分处形成从半导体衬底的表面相对较低的高度。

公开(公告)号：US4683838A

公开(公告)日：1987-08-04

申请号：US750474

申请日：1985-07-01

申请人： Shin-Ichiro Kimura ,  Eiichi Murakami ,  Terunori Warabisako ,  Kiyoshi Miyake ,  Hideo Sunami

发明人： Shin-Ichiro Kimura ,  Eiichi Murakami ,  Terunori Warabisako ,  Kiyoshi Miyake ,  Hideo Sunami

IPC分类号： H01L21/302 ,  C23C14/22 ,  C23C14/32 ,  H01J37/32 ,  H01L21/3065 ,  C23C16/00

CPC分类号： H01J37/32623 ,  C23C14/22 ,  C23C14/32 ,  H01J37/3266

摘要： An insulator film can be formed at a low temperature without any damage to a substrate to be treated by a plasma in a plasma treatment system which comprises a magnetron for generating a microwave, an isolator for isolating a wave guide from the magnetron, a discharge tube for generating a plasma, the wave guide for leading the microwave from the magnetron to the discharge tube, a vacuum chamber integrally formed together with the discharge tube, an evaporation source provided in the vacuum chamber, a substrate to be treated and provided at a position to sandwich a stream of the plasma between the substrate and the evaporation source, electromagnets provided around the discharge tube and the vacuum chamber, and a manipulator for manipulating the substrate, the electromagnets generating a magnetic field to confine the stream of the plasma.

摘要翻译： 可以在低温下形成绝缘膜，而不会对包括用于产生微波的磁控管的等离子体处理系统中的等离子体处理的基板造成任何损坏，用于将波导从磁控管隔离的隔离器，放电管 用于产生等离子体，用于将微波从磁控管引导到放电管的波导，与放电管一体形成的真空室，设置在真空室中的蒸发源，待处理的基板，并设置在位置 在基板和蒸发源之间夹着等离子体流，设置在放电管和真空室周围的电磁体以及用于操纵基板的操纵器，电磁体产生磁场以限制等离子体的流。

公开(公告)号：US20100105199A1

公开(公告)日：2010-04-29

申请号：US12652517

申请日：2010-01-05

申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC分类号： H01L21/28

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

摘要翻译： 提供一种制造非挥发性半导体存储器件的方法，其克服了由于最佳栅极高度的不同而引入的注入离子的问题，同时形成利用侧壁结构的自对准分裂栅型存储单元和 缩放MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

公开(公告)号：US08324092B2

公开(公告)日：2012-12-04

申请号：US12652517

申请日：2010-01-05

申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC分类号： H01L21/00

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

摘要翻译： 提供一种制造非挥发性半导体存储器件的方法，其克服了由于最佳栅极高度的差异而引入的离子的渗透问题，同时形成利用侧壁结构的自对准分裂栅型存储单元和 缩放MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

公开(公告)号：US06661048B2

公开(公告)日：2003-12-09

申请号：US09825921

申请日：2001-04-05

申请人： Toshiaki Yamanaka ,  Shin′ichiro Kimura ,  Hideyuki Matsuoka ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Kiyoo Itoh

发明人： Toshiaki Yamanaka ,  Shin′ichiro Kimura ,  Hideyuki Matsuoka ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Kiyoo Itoh

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.

摘要翻译： 根据本发明，确保了覆盖边缘，用于使布线电极11与电容器的接触点处的存储电极15匹配，并且可以通过将氮化钛的插头电极11放置在存储单元的所需区域 在半导体基板的有源区域或栅电极的上方，减小用于使层叠结构的电容器的存储电极15通过的开口的尺寸，并且减小布线电极13的线宽。通常使用 外围电路中的CMISFET区域和静态RAM的存储单元中的上述插头电极，可以使其电路布局紧凑。

公开(公告)号：US4882289A

公开(公告)日：1989-11-21

申请号：US184786

申请日：1988-04-22

申请人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

发明人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/105 ,  Y10S438/911

摘要： A semiconductor memory wherein a memory cell region having a plurality of memory cells and has higher altitude from the surface of semiconductor substrate is formed in the recessed part of semiconductor substrate having the recessed part and projected part and a peripheral circuit region which is comparatively low from the surface of semiconductor substrate is formed to the projected part of semiconductor substrate.

摘要翻译： 一种半导体存储器，其中具有多个存储单元并且具有来自半导体衬底的表面的较高高度的存储单元区域形成在具有凹陷部分和突起部分的半导体衬底的凹部中，并且外围电路区域相对较低 半导体衬底的表面形成在半导体衬底的突出部分上。

公开(公告)号：US20070145455A1

公开(公告)日：2007-06-28

申请号：US11452256

申请日：2006-06-14

申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-ichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-ichiro Kimura

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

摘要翻译： 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而导致的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

公开(公告)号：US06576510B2

公开(公告)日：2003-06-10

申请号：US09826088

申请日：2001-04-05

申请人： Toshiaki Yamanaka ,  Shin' ichiro Kimura ,  Hideyuki Matsuoka ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Kiyoo Itoh

发明人： Toshiaki Yamanaka ,  Shin' ichiro Kimura ,  Hideyuki Matsuoka ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Kiyoo Itoh

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.

摘要翻译： 根据本发明，确保了覆盖边缘，用于使布线电极11与电容器的接触点处的存储电极15匹配，并且可以通过将氮化钛的插头电极11放置在存储单元的所需区域 在半导体基板的有源区域或栅电极的上方，减小用于使层叠结构的电容器的存储电极15通过的开口的尺寸，并且减小布线电极13的线宽。通过共同使用 外围电路中的CMISFET区域和静态RAM的存储单元中的上述插头电极，可以使其电路布局紧凑。