Invention Grant
- Patent Title: Integrated circuit device including a layered superlattice material with an interface buffer layer
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Application No.: US10262003Application Date: 2002-09-30
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Publication No.: US06605477B2Publication Date: 2003-08-12
- Inventor: Kiyoshi Uchiyama
- Applicant: Kiyoshi Uchiyama
- Main IPC: H01L2100
- IPC: H01L2100

Abstract:
An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.
Public/Granted literature
- US20030034509A1 Integrated circuit device including a layered superlattice material with an interface buffer layer Public/Granted day:2003-02-20
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