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    Semiconductor memory device, method for driving the same and method for fabricating the same
    2.
    发明授权
    Semiconductor memory device, method for driving the same and method for fabricating the same 失效
    半导体存储器件，其驱动方法及其制造方法

    公开(公告)号：US06580632B2

    公开(公告)日：2003-06-17

    申请号：US09782300

    申请日：2001-02-14

    Applicant: Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

    Inventor： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

    IPC: G11C1122

    CPC classification number: H01L29/516 ,  G11C11/22 ,  G11C11/223 ,  H01L29/78391

    Abstract: Data is read out from a ferroelectric film with its remnant polarization associated with one of two possible logical states of the data and with a bias voltage applied to a control gate electrode over the ferroelectric film. The ferroelectric film creates either up or down remnant polarization. So the down remnant polarization may represent data “1” while the up or almost zero remnant polarization may represent data “0”, for example. By regarding the almost zero remnant polarization state as representing data “0”, a read current value becomes substantially constant in the data “0” state. As a result, the read accuracy improves. Also, if imprinting of one particular logical state (e.g., data “1”) is induced in advance, then the read accuracy further improves.

    Abstract translation: 从强电介质薄膜读​​出数据，其剩余极化与数据的两种可能的逻辑状态之一相关，并且施加到铁电体膜上的控制栅电极上的偏置电压。 铁电薄膜产生上或下残余极化。 因此，向下残留极化可以表示数据“1”，而上或近零残余极化例如可以表示数据“0”。 通过将几乎为零的残余极化状态作为表示数据“0”，读取的电流值在数据“0”状态下变得基本恒定。 结果，读取精度提高。 此外，如果预先诱导一个特定逻辑状态（例如，数据“1”）的印记，则读取精度进一步提高。

    Chemical vapor deposition process for fabricating layered superlattice materials
    5.
    发明授权
    Chemical vapor deposition process for fabricating layered superlattice materials 有权

    公开(公告)号：US06562678B1

    公开(公告)日：2003-05-13

    申请号：US09521094

    申请日：2000-03-07

    Applicant: Kiyoshi Uchiyama ,  Narayan Solayappan ,  Carlos A. Paz de Araujo

    Inventor： Kiyoshi Uchiyama ,  Narayan Solayappan ,  Carlos A. Paz de Araujo

    IPC: H01L218242

    CPC classification number: C23C16/45561 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/44 ,  Y10S438/935 ,  Y10S438/938

    Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

    Integrated circuit device including a layered superlattice material with an interface buffer layer
    6.
    发明授权
    Integrated circuit device including a layered superlattice material with an interface buffer layer 失效
    集成电路装置，包括具有界面缓冲层的分层超晶格材料

    公开(公告)号：US06489645B1

    公开(公告)日：2002-12-03

    申请号：US09898927

    申请日：2001-07-03

    Applicant: Kiyoshi Uchiyama

    Inventor： Kiyoshi Uchiyama

    IPC: H01L2976

    CPC classification number: H01L21/02197 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/56

    Abstract: An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.

    Abstract translation: 集成电路存储器件包括薄膜层状超晶格材料层和电极。 在所述薄膜层状超晶格材料层和所述电极之间形成界面缓冲层。 界面缓冲层选自：1）A位或B位金属的简单氧化物，不包括铋; 和2）与第一层状超晶格材料不同的第二层超晶格材料，并且在第一层状超晶格材料中含有与A位或B位金属相同的至少一个A位或B位金属。 不包括铋的氧化物可以是包括多种金属的复合氧化物或仅包括一种金属的简单氧化物。 最优选的界面缓冲层选自钽酸锶，钽酸铋，钽酸锶铌酸铌，铌酸铋铋，二氧化钛，五氧化二钽，A位和B位金属的其它简单氧化物，以及 一个或多个A位或B位金属的其它简单氧化物。

    Semiconductor memory and method of driving semiconductor memory
    7.
    发明授权
    Semiconductor memory and method of driving semiconductor memory 失效
    半导体存储器和驱动半导体存储器的方法

    公开(公告)号：US06396095B1

    公开(公告)日：2002-05-28

    申请号：US09869522

    申请日：2001-06-29

    Applicant: Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

    Inventor： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

    IPC: H01L2976

    CPC classification number: G11C11/22 ,  H01L21/28291 ,  H01L29/42324 ,  H01L29/516 ,  H01L29/78391

    Abstract: Source/drain regions for a field effect transistor are defined in a semiconductor substrate with a channel region interposed therebetween. A first gate electrode is formed over the semiconductor substrate with an insulating film sandwiched therebetween and has a gate length shorter than the length of the channel region. A ferroelectric film is formed to cover the first gate electrode and to have both side portions thereof make contact with the insulating film. A second gate electrode is formed to cover the ferroelectric film.

    Abstract translation: 用于场效应晶体管的源极/漏极区限定在其间插入沟道区的半导体衬底中。 第一栅电极形成在半导体衬底之上，绝缘膜夹在其间，栅极长度短于沟道区的长度。 形成铁电膜以覆盖第一栅电极并且使其两侧部分与绝缘膜接触。 形成第二栅电极以覆盖铁电体膜。

    Tunneling transistor applicable to nonvolatile memory
    8.
    发明授权
    Tunneling transistor applicable to nonvolatile memory 失效
    隧道晶体管适用于非易失性存储器

    公开(公告)号：US06351004B1

    公开(公告)日：2002-02-26

    申请号：US09688494

    申请日：2000-10-16

    Applicant: Yasuhiro Shimada ,  Shinichiro Hayashi ,  Kiyoshi Uchiyama ,  Keisuke Tanaka

    Inventor： Yasuhiro Shimada ,  Shinichiro Hayashi ,  Kiyoshi Uchiyama ,  Keisuke Tanaka

    IPC: H01L2978

    CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L29/772 ,  H01L29/78391

    Abstract: A tunneling transistor is provided as an effective means for miniaturization of a semiconductor integrated circuit having nonvolatile memory. An insulating layer is disposed on a silicon substrate. A source and a drain are disposed on the insulating layer, with an insulator of a few nanometers in thickness that provides a tunnel barrier being interposed between the source and the drain. A ferroelectric layer that exhibits spontaneous polarization is disposed directly above a region of the source that is adjacent to the insulator. With this construction, when the ferroelectric layer is polarized in a predetermined direction, at least a portion of the region of the source adjacent to the insulator forms a depletion region, with it being possible to vary the amount of current tunneling through the insulator depending on whether the ferroelectric layer is polarized or not.

    Abstract translation: 提供隧道晶体管作为具有非易失性存储器的半导体集成电路的小型化的有效手段。 绝缘层设置在硅衬底上。 源极和漏极设置在绝缘层上，具有几纳米厚度的绝缘体，其提供了在源极和漏极之间插入的隧道势垒。 显示自发极化的铁电层直接设置在与绝缘体相邻的源极的正上方。 利用这种结构，当铁电层在预定方向上极化时，与绝缘体相邻的源极的区域的至少一部分形成耗尽区，根据该结构，可以改变通过绝缘体的电流隧穿量 铁电层是否极化。

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