Invention Grant
US06608771B2 Low-power circuit structures and methods for content addressable memories and random access memories 失效
用于内容可寻址存储器和随机存取存储器的低功率电路结构和方法

Low-power circuit structures and methods for content addressable memories and random access memories
Abstract:
A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits.
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