公开(公告)号：US06952113B2

公开(公告)日：2005-10-04

申请号：US10644211

申请日：2003-08-20

Applicant: Richard B. Brown ,  Ching-Te K. Chuang ,  Peter W. Cook ,  Koushik K. Das ,  Rajiv V. Joshi

Inventor： Richard B. Brown ,  Ching-Te K. Chuang ,  Peter W. Cook ,  Koushik K. Das ,  Rajiv V. Joshi

IPC: H03K19/00 ,  A03K19/003

CPC classification number: H03K19/0016

Abstract: A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETs) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.

Abstract translation: 具有降低的亚阈值泄漏的多阈值集成电路（IC）和减少泄漏的方法。 电路逻辑电路和电源连接（V SUB）和GND之间的可选供电开关器件（NFET和/或PFET）的电路具有比正常电路器件更高的阈值。 当供电开关装置打开时，一些装置可能具有降低的阈值。 具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。 或者，可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。 中间电源连接在器件上可能具有去耦电容，器件可以锥形化，以获得最佳堆叠高度和最佳锥度比，以最大限度地减少电路泄漏和电路延迟。

公开(公告)号：US06848060B2

公开(公告)日：2005-01-25

申请号：US09794467

申请日：2001-02-27

Applicant: Peter W. Cook ,  Stanley E. Schuster

Inventor： Peter W. Cook ,  Stanley E. Schuster

IPC: G06F13/42 ,  G06F9/38 ,  G06F3/00

CPC classification number: G06F9/3869 ,  G06F9/3871

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

Abstract translation: 同步和异步数据传输之间的接口包括彼此耦合以形成用于数据传输的流水线的多个级。 多级包括执行与异步数据传送同步的第一级，至异步数据传输异步的至少一个中间级和执行异步到同步数据传输的最后级。 同步时钟路径在多个级上传播定时信号，以便当定时信号存在于该级时使第一级和最后级能够执行操作。

公开(公告)号：US06608771B2

公开(公告)日：2003-08-19

申请号：US09933189

申请日：2001-08-20

Applicant: Hans M. Jacobson ,  Prabhakar N. Kudva ,  Stanley Everett Schuster ,  Peter W. Cook

Inventor： Hans M. Jacobson ,  Prabhakar N. Kudva ,  Stanley Everett Schuster ,  Peter W. Cook

IPC: G11C1500

CPC classification number: G11C15/04

Abstract: A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits.

Abstract translation: 提供了一种用于将地址与数据相关联的方法。 该方法包括将连接到多个标签匹配功能的匹配线预先充电到第一电位，其中每个标签匹配功能包括一个或多个匹配逻辑器件，将用于第一标签位的两个标签行放电到地，以及读取多个标签 位和相应的数据位分别分配到多个标签行和多条数据线上。 该方法还包括确定标签位和数据位之间的匹配，并且在确定每个标签位的匹配时，将匹配线拉到第二电位。

公开(公告)号：US06512397B1

公开(公告)日：2003-01-28

申请号：US09933188

申请日：2001-08-20

Applicant: Hans M. Jacobson ,  Prabhakar N. Kudva ,  Peter W. Cook ,  Stanley Everett Schuster

Inventor： Hans M. Jacobson ,  Prabhakar N. Kudva ,  Peter W. Cook ,  Stanley Everett Schuster

IPC: H03K1720

CPC classification number: G06F13/14 ,  Y02D10/14

Abstract: A method is provided for selecting a participant to issue. The method includes signaling a domino OR gate arbitration device upon a ready request of a participant having a priority, determining within the domino OR gate arbitration device the relative priority of the participant, signaling the domino OR gate arbitration device through an any-request device upon the ready request of a higher priority participant, and issuing the higher priority participant upon determining the higher priority participant to have a priority highest among participants ready for issue. The method includes gating one of a precharge signal and an evaluate signal of the precharged domino OR gate arbitration device by the ready request of the participant. The method further includes latching a result of the domino OR gate arbitration device and a clock signal, and gating the clock signal by the ready signal of the participant.

Abstract translation: 提供了一种用于选择参与者发行的方法。 该方法包括在具有优先权的参与者的就绪请求之后发信号通知多米诺骨牌或门仲裁装置，在多米诺诺或门仲裁装置内确定参与者的相对优先级，通过任何请求装置向多米诺骨牌或门仲裁装置发信号 确定较高优先权的参与者的准备好的请求，并且在确定较高优先权的参与者之后发出优先权较高的参与者以便在准备发行的参与者中具有最高优先权。 该方法包括通过参与者的就绪请求选通预充电多米诺OR门仲裁装置的预充电信号和评估信号之一。 该方法还包括锁存多米诺OROR仲裁装置的结果和时钟信号，并通过参与者的就绪信号门控时钟信号。

公开(公告)号：US5148059A

公开(公告)日：1992-09-15

申请号：US679363

申请日：1991-04-02

Applicant: Chih-Liang Chen ,  Peter W. Cook ,  Lewis M. Terman

Inventor： Chih-Liang Chen ,  Peter W. Cook ,  Lewis M. Terman

IPC: H03K19/0175 ,  H03K19/08 ,  H03K19/086 ,  H03K19/0944

CPC classification number: H03K19/09448 ,  H03K19/017527 ,  H03K19/086

Abstract: An ECL circuit (12) for directly coupling to and from a CMOS circuit (10). The ECL circuit has an input node for receiving an input signal generated by a CMOS circuit. The input signal swings, or transitions, between a first potential (V.sub.0) and a second potential (V.sub.1). The ECL circuit further includes ECL core circuitry (Q.sub.3, Q.sub.4, R.sub.L), coupled to the input node and responsive the received signal, for generating an intermediate electrical signal that swings between a third potential (V.sub.2) and a fourth potential (V.sub.3) that is approximately two times (V.sub.1 -V.sub.0). The ECL circuit further includes an output driver circuit for coupling to an input of a CMOS circuit or to another ECL circuit. The output driver circuit has an input node coupled to an output of the ECL core circuitry and includes emitter followers (EF.sub.1, EF.sub.2) for generating, in response to the intermediate electrical signal swinging between V.sub.2 and V.sub.3, a first output signal tha swings between the V.sub.0 and V.sub.1.

Abstract translation: 用于直接耦合到CMOS电路（10）的ECL电路（12）。 ECL电路具有用于接收由CMOS电路产生的输入信号的输入节点。 输入信号在第一电位（V0）和第二电位（V1）之间摆动或转变。 ECL电路还包括耦合到输入节点并响应于接收信号的ECL核心电路（Q3，Q4，RL），用于产生在第三电位（V2）和第四电位（V3）之间摆动的中间电信号， 大约是两倍（V1-V0）。 ECL电路还包括用于耦合到CMOS电路的输入或另一ECL电路的输出驱动器电路。 输出驱动器电路具有耦合到ECL核心电路的输出的输入节点，并且包括发射极跟随器（EF1，EF2），用于响应于V2和V3之间的中间电信号摆动而产生第一输出信号， V0和V1。

公开(公告)号：US4504924A

公开(公告)日：1985-03-12

申请号：US392828

申请日：1982-06-28

Applicant: Peter W. Cook ,  Hung-Hui Hsieh ,  Glen S. Miranker

Inventor： Peter W. Cook ,  Hung-Hui Hsieh ,  Glen S. Miranker

IPC: H03K19/173 ,  G06F7/50 ,  G06F7/505 ,  G06F7/506 ,  G06F7/508

CPC classification number: G06F7/505

Abstract: Complex logical mechanism, for simultaneously producing output signals related logically to a set of input signals, implemented in transfer gate pairs. The first transfer gate of each pair is connected generally in series and is controlled by conduction according to the signals applied. The second transfer gate of each pair shunts the output node of its related first transfer gate to ground, when enabled by a control signal complementary to the data pattern applied to the first transfer gate of the pair. This direct control of line voltages affirmatively drives the lines or affirmatively grounds the lines to eliminate back circuits.Carry propagation to higher order bit positions is along carry propagate lines, with series connected carry propagate first transfer gates. Order positions not having data values appropriate for carry propagation do not transmit carry values--these transfer gates are not controlled for conduction, but are nonetheless subject to possible back circuits. Carry propagate negation second transfer gates, connected in respective pairs with the carry propagate first transfer gates, are controlled by signals complementary to the control signals for the respectively carry propagate transfer gates, and, when enabled, connect the output nodes of the respective carry propagate first transfer gates directly to ground reference potential.

Abstract translation: 复杂的逻辑机制，用于同时产生与传输门对实现的一组输入信号逻辑相关的输出信号。 每对的第一传输门通常串联连接，并根据施加的信号通过导通来控制。 当通过与施加到该对的第一传输门的数据模式互补的控制信号使能时，每对的第二传输门将其相关的第一传输门的输出节点分流到地。 线路电压的这种直接控制肯定地驱动线路或肯定地使线路消除反向电路。 携带传播到较高位位置沿着传播线，串联连接传播第一传输门。 没有适合于进位传播的数据值的顺序位置不传送进位值 - 这些传送门不受控制用于传导，但仍然受到可能的反向电路的影响。 携带传播第二传输门，与进位传播第一传输门分别成对连接，由与分别传送传输门的控制信号互补的信号控制，并且当使能时，连接各个传送传播的输出节点 第一传输门直接到地参考电位。

公开(公告)号：US07308593B2

公开(公告)日：2007-12-11

申请号：US11376544

申请日：2006-03-14

Applicant: Hans M. Jacobson ,  Prabhakar N. Kudva ,  Pradip Bose ,  Peter W. Cook ,  Stanley E. Schuster

Inventor： Hans M. Jacobson ,  Prabhakar N. Kudva ,  Pradip Bose ,  Peter W. Cook ,  Stanley E. Schuster

IPC: H04L5/00 ,  G06F9/30

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G06F9/3871 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14

Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

Abstract translation: 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

公开(公告)号：US07134028B2

公开(公告)日：2006-11-07

申请号：US10428170

申请日：2003-05-01

Applicant: Pradip Bose ,  David M. Brooks ,  Peter W. Cook ,  Philip G. Emma ,  Michael K. Gschwind ,  Stanley E. Schuster ,  Vijayalakshmi Srinivasan

Inventor： Pradip Bose ,  David M. Brooks ,  Peter W. Cook ,  Philip G. Emma ,  Michael K. Gschwind ,  Stanley E. Schuster ,  Vijayalakshmi Srinivasan

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F9/3869 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.

Abstract translation: 包括单元功率控制的集成电路（IC），用于可控地减少IC中的LdI / dt噪声的泄漏功率的泄漏降低电路，以及在IC单元中调用主动/休眠状态的活动预测单元。 预测单元确定每个IC单元的导通和关闭时间。 预测单元控制电源电压选择电路，其在预测的导通时间选择性地将电源电压传递到单独的电源线，并且在预测的关断时间选择性地阻断电源电压。

公开(公告)号：US4931971A

公开(公告)日：1990-06-05

申请号：US297170

申请日：1989-01-13

Applicant: Peter W. Cook ,  Robert K. Montoye

Inventor： Peter W. Cook ,  Robert K. Montoye

IPC: G06F5/01 ,  G06F7/00 ,  G06F7/76

CPC classification number: G06F5/015

Abstract: A data shifter/rotator which is comprised of two levels of s, where s is an integer >2, way switches. The outputs of the first level are connected to the corresponding inputs of the second level. There are first and second control words, with the first control word controlling the amount of the shift/rotation in the first level, and the second control word controlling the amount of the shift/rotation in the second level. The amount of the shift/rotation is determined by the position of the s way switches in each level, as selected by the respective control words.

公开(公告)号：US4199695A

公开(公告)日：1980-04-22

申请号：US883429

申请日：1978-03-03

Applicant: Peter W. Cook ,  Stanley E. Schuster

Inventor： Peter W. Cook ,  Stanley E. Schuster

IPC: H01L27/04 ,  G06F1/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/082 ,  H03K19/003 ,  H03K19/017 ,  H03K3/353

CPC classification number: H03K5/023 ,  G06F1/04 ,  H01L27/06 ,  H01L29/78 ,  H03K17/0822 ,  H03K19/00315 ,  H03K19/01714

Abstract: An improved field effect transistor circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers. The circuit comprises a voltage control means adapted to maintain a simultaneous gate and drain to source voltage of FET devices within a characteristic hot electron operational voltage range. The voltage control means is adapted to reduce FET drain to source voltage by connecting a plurality of FET devices in series to reduce the drain to source voltage drop across each device. The drain to source voltage is further defined by connecting the common nodes of successive series connected devices to a specified voltage source that is less than a characteristic hot electron drain to source voltage. The voltage control means also includes a gate voltage clamping FET that is adapted to hold down the gate of a device when the drain to source voltage of the device rises above a particular hot electron voltage. The voltage control means further comprises a plurality of timing pulses that define particular combinations of gate and drain to source device voltages that are less than characteristic combined hot electron voltages. The voltage control means further includes devices with width to length ratios adapted to provide close voltage tracking between input drain voltages and output source voltages to maintain a minimum drain to source voltage drop. The operation of the hot electron voltage control means is particularly described with respect to embodiments using voltage stressed bootstrap driver FETs to generate on chip clock phases.

Abstract translation: 一种改进的场效应晶体管电路，适于在高开关速度下工作并避免受压应力FET自举驱动器的热电子操作。 该电路包括电压控制装置，其适于在特征热电子工作电压范围内保持FET器件的同时栅极和漏极到源极电压。 电压控制装置适于通过串联连接多个FET器件来减少FET漏极到源极电压，以减少跨越每个器件的漏极到源极电压降。 通过将连续串联连接的器件的公共节点连接到小于特征热电子漏极到源极电压的指定电压源，进一步限定漏极到源极电压。 电压控制装置还包括栅极电压钳位FET，其适于在器件的漏极 - 源极电压升高到特定热电子电压之上时压住器件的栅极。 电压控制装置还包括多个定时脉冲，其限定小于特征组合热电子电压的栅极和漏极与源极器件电压的特定组合。 电压控制装置还包括宽度与长度比适合于在输入漏极电压和输出源电压之间提供紧密电压跟踪的装置，以保持对源极电压降的最小漏极。 关于使用电压应力自举驱动器FET以产生片上时钟相位的实施例，特别描述了热电子电压控制装置的操作。