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公开(公告)号：US09632778B2
公开(公告)日：2017-04-25
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.
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公开(公告)号：US09575756B2
公开(公告)日：2017-02-21
申请号：US13569349
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/3879 , G06F9/3887 , G06F15/8084 , G11C7/1006 , G11C8/12
摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a system for vector processor predication in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.
摘要翻译： 实施例涉及有源存储器件中的矢量处理器预测。 一个方面包括用于有源存储器设备中的向量处理器预测的系统。 该系统包括有源存储器设备中的存储器和有源存储器设备中的处理元件。 处理单元被配置为执行包括用多个子指令解码指令并行执行的方法。 一个或多个掩码位从处理元件中的向量掩码寄存器访问。 一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。
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公开(公告)号：US09569211B2
公开(公告)日：2017-02-14
申请号：US13566129
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/3879 , G06F9/3887 , G06F15/8084 , G11C7/1006 , G11C8/12
摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.
摘要翻译： 实施例涉及有源存储器件中的矢量处理器预测。 一个方面包括一种用于包括存储器和处理元件的有源存储器件中的向量处理器预测的方法。 该方法包括在处理元件中解码包括并行执行的多个子指令的指令。 一个或多个掩码位从处理元件中的向量掩码寄存器访问。 一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。
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公开(公告)号：US20140040601A1
公开(公告)日：2014-02-06
申请号：US13566129
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/3879 , G06F9/3887 , G06F15/8084 , G11C7/1006 , G11C8/12
摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.
摘要翻译： 实施例涉及有源存储器件中的矢量处理器预测。 一个方面包括一种用于包括存储器和处理元件的有源存储器件中的向量处理器预测的方法。 该方法包括在处理元件中解码包括并行执行的多个子指令的指令。 一个或多个掩码位从处理元件中的向量掩码寄存器访问。 一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。
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公开(公告)号：US08564262B2
公开(公告)日：2013-10-22
申请号：US12944392
申请日：2010-11-11
IPC分类号： G05G1/56
摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.
摘要翻译： 提供电源门控或旁路电压调节器的机制。 响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得 基本上没有电压被第一电路输出到主输出节点。 响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上 电压源的电压由第一电路输出到主输出节点。
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公开(公告)号：US07685457B2
公开(公告)日：2010-03-23
申请号：US11846847
申请日：2007-08-29
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译： 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。
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7.发明授权Method of stalling one or more stages in an interlocked synchronous pipeline 有权在联锁同步管道中停止一个或多个阶段的方法公开(公告)号：US07475227B2
公开(公告)日：2009-01-06
申请号：US11375989
申请日：2006-03-14
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： A method of operating an integrated circuit including a pipeline and a method of stalling stages in the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译： 一种操作包括流水线的集成电路的方法和在管线中停止级的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。
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公开(公告)号：US07076681B2
公开(公告)日：2006-07-11
申请号：US10187698
申请日：2002-07-02
申请人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
发明人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
IPC分类号： G06F1/04
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3802 , G06F9/3836 , G06F9/384 , G06F9/3867 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
摘要翻译： 同步集成电路，如标量处理器或超标量处理器。 电路组件或单元由公共系统时钟计时并同步。 至少两个时钟单元包括多个寄存器级，例如流水线级。 每个时钟单元中的本地时钟发生器将来自一个或多个其他单元的公共系统时钟和失速状态相结合，以调整寄存器时钟频率向上或向下。
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9.发明授权公开(公告)号：US06946869B2
公开(公告)日：2005-09-20
申请号：US10685863
申请日：2003-10-15
申请人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
发明人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
CPC分类号： H03K19/0016
摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.
摘要翻译： 泄漏电流控制装置包括在序列中执行功能的数据路径中具有一个或多个功能的电路。 每个功能具有功率降低逻辑以激励每个相应的功能。 泄漏控制电路与功率降低逻辑相互作用，使得功能在控制序列中被激励或断电，使得数据驻留的功能被激励，并且其他功能中的至少一个没有通电。
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公开(公告)号：US20140047214A1
公开(公告)日：2014-02-13
申请号：US13570372
申请日：2012-08-09
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
CPC分类号： G06F15/8076 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/34 , G06F9/345
摘要： An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder.
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