- 专利标题: Method for low topography semiconductor device formation
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申请号: US09864033申请日: 2001-05-23
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公开(公告)号: US06624486B2公开(公告)日: 2003-09-23
- 发明人: David B. Colavito , Nivo Rovedo , Phung T. Nguyen
- 申请人: David B. Colavito , Nivo Rovedo , Phung T. Nguyen
- 主分类号: H01L2976
- IPC分类号: H01L2976
摘要:
A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.
公开/授权文献
- US20020175369A1 Method for low topography semiconductor device formation 公开/授权日:2002-11-28
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