公开(公告)号：US20100059764A1

公开(公告)日：2010-03-11

申请号：US12618152

申请日：2009-11-13

Applicant: Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

Inventor： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636

Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

Abstract translation: 提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。 本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。 本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。 第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除 或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

公开(公告)号：US07618866B2

公开(公告)日：2009-11-17

申请号：US11423227

申请日：2006-06-09

Applicant: Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

Inventor： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636

Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

Abstract translation: 提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。 本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。 本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。 第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除 或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

公开(公告)号：US07442619B2

公开(公告)日：2008-10-28

申请号：US11383965

申请日：2006-05-18

Applicant: Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

Inventor： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC: H01L21/283 ,  H01L23/482

CPC classification number: H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the substantially L-shaped silicide element includes a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

Abstract translation: 公开了一种制造具有形成接触的大致L形硅化物元件的半导体器件的方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，基本上L形的硅化物元件包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触 STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US07279758B1

公开(公告)日：2007-10-09

申请号：US11420047

申请日：2006-05-24

Applicant: Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

Inventor： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

Abstract: The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract translation: 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括均包含碳取代和拉伸应力单晶半导体的第一和第二图案应力层。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

公开(公告)号：US06797569B2

公开(公告)日：2004-09-28

申请号：US10249917

申请日：2003-05-19

Applicant: David B. Colavito ,  Nivo Rovedo ,  Phung T. Nguyen

Inventor： David B. Colavito ,  Nivo Rovedo ,  Phung T. Nguyen

IPC: H01L21336

CPC classification number: H01L29/66613 ,  H01L21/28114 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7835

Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

Abstract translation: 公开了一种形成平面化场效应晶体管（FET）的方法。 在本发明的示例性实施例中，所述方法包括在衬底上限定有源半导体区域，所述有源半导体区域还包括一对台面区域。 源区域被限定在一对台面区域之一的顶表面内，并且漏区域限定在该对台面区域中另一个的顶表面内。 然后，在一对台面区域之间沉积栅极材料，并且栅极材料被平坦化以形成栅极。 由此，栅极的顶表面与源极和漏极区域基本上是平面的。

公开(公告)号：US06352903B1

公开(公告)日：2002-03-05

申请号：US09605730

申请日：2000-06-28

Applicant: Nivo Rovedo ,  David B. Colavito

Inventor： Nivo Rovedo ,  David B. Colavito

IPC: H01L2120

CPC classification number: H01L29/41783 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/41766

Abstract: In a bulk silicon process, an insulating layer is placed under the portion of the source and drain used for contacts, thereby reducing junction capacitance. The processing involves a smaller than usual transistor area that is not large enough to hold the contacts, which are placed in an aperture cut into the shallow trench isolation.

Abstract translation: 在体硅工艺中，将绝缘层放置在用于触点的源极和漏极部分之下，从而减少结电容。 该处理涉及比通常的不足够大的晶体管面积，以保持接触，其被放置在切割成浅沟槽隔离的孔中。

公开(公告)号：US4729006A

公开(公告)日：1988-03-01

申请号：US840180

申请日：1986-03-17

Applicant: Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

Inventor： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06 ,  H01L29/34 ,  H01L29/78

CPC classification number: H01L21/76224

Abstract: A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

Abstract translation: 一种用于在用于制造CMOS集成电路的半导体上形成完全凹陷（平面）隔离区域的方法，所得到的半导体结构包括在其中形成有台面的P掺杂硅衬底中，形成接触的硼硅酸盐玻璃的低粘度侧壁间隔物 其中所述台面的侧壁被指定为在其中形成有N沟道器件; 然后用TEOS填充与台面相邻的基板中的沟槽; 并加热该结构直到侧壁间隔物中的硼扩散到指定台面的侧壁中以形成通道停止点。 这些侧壁间隔件通过减轻TEOS中的内部机械应力来减少TEOS中的裂纹的发生，并允许通过扩散形成通道停止，从而允许台面壁基本上垂直。

公开(公告)号：US4671851A

公开(公告)日：1987-06-09

申请号：US791861

申请日：1985-10-28

Applicant: Klaus D. Beyer ,  James S. Makris ,  Eric Mendel ,  Karen A. Nummy ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

Inventor： Klaus D. Beyer ,  James S. Makris ,  Eric Mendel ,  Karen A. Nummy ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

CPC classification number: H01L21/763 ,  H01L21/31053 ,  H01L21/743 ,  H01L21/76202

Abstract: A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based slurry. The Si.sub.3 N.sub.4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si.sub.3 N.sub.4 layer located on the top and at the sidewalls of the "bird's heads" and the underlying SiO.sub.2 protuberances are removed to provide a substantially planar integrated structure.

Abstract translation: 用于去除硅片表面的SiO 2突起的化学机械（化学机械）方法，包括“鸟头”的突起。 将Si 3 N 4的薄的蚀刻停止层沉积在晶片表面上，然后用SiO 2水基浆料进行化学研磨。 Si 3 N 4仅在晶片表面的平面部分上用作抛光或蚀刻阻挡层。 位于“鸟头”顶部和侧壁处的Si 3 N 4层的部分和下面的SiO 2突起被去除以提供基本平坦的整体结构。

公开(公告)号：US20120217585A1

公开(公告)日：2012-08-30

申请号：US13468270

申请日：2012-05-10

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L27/088

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US08232151B2

公开(公告)日：2012-07-31

申请号：US13167303

申请日：2011-06-23

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。