公开(公告)号：US06624486B2

公开(公告)日：2003-09-23

申请号：US09864033

申请日：2001-05-23

申请人： David B. Colavito ,  Nivo Rovedo ,  Phung T. Nguyen

发明人： David B. Colavito ,  Nivo Rovedo ,  Phung T. Nguyen

IPC分类号： H01L2976

CPC分类号： H01L29/66613 ,  H01L21/28114 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7835

摘要： A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

公开(公告)号：US06797569B2

公开(公告)日：2004-09-28

申请号：US10249917

申请日：2003-05-19

申请人： David B. Colavito ,  Nivo Rovedo ,  Phung T. Nguyen

发明人： David B. Colavito ,  Nivo Rovedo ,  Phung T. Nguyen

IPC分类号： H01L21336

CPC分类号： H01L29/66613 ,  H01L21/28114 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7835

摘要： A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

摘要翻译： 公开了一种形成平面化场效应晶体管（FET）的方法。 在本发明的示例性实施例中，所述方法包括在衬底上限定有源半导体区域，所述有源半导体区域还包括一对台面区域。 源区域被限定在一对台面区域之一的顶表面内，并且漏区域限定在该对台面区域中另一个的顶表面内。 然后，在一对台面区域之间沉积栅极材料，并且栅极材料被平坦化以形成栅极。 由此，栅极的顶表面与源极和漏极区域基本上是平面的。

公开(公告)号：US06352903B1

公开(公告)日：2002-03-05

申请号：US09605730

申请日：2000-06-28

申请人： Nivo Rovedo ,  David B. Colavito

发明人： Nivo Rovedo ,  David B. Colavito

IPC分类号： H01L2120

CPC分类号： H01L29/41783 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/41766

摘要： In a bulk silicon process, an insulating layer is placed under the portion of the source and drain used for contacts, thereby reducing junction capacitance. The processing involves a smaller than usual transistor area that is not large enough to hold the contacts, which are placed in an aperture cut into the shallow trench isolation.

摘要翻译： 在体硅工艺中，将绝缘层放置在用于触点的源极和漏极部分之下，从而减少结电容。 该处理涉及比通常的不足够大的晶体管面积，以保持接触，其被放置在切割成浅沟槽隔离的孔中。