A method of fabricating flash memory cell is described. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer; forming a buffer layer; removing portions of the buffer layer to farm a floating gate insulating layer; forming a second conductive layer; removing portions of the first conductive layer and the second conductive layer, such that the second conductive layer forms conductive spacers having conductive tips situated at the tips, and the floating gate insulating layer, the floating gate and the first gate insulating layer are combined as a floating gate region; forming a second insulating layer; forming a third conductive layer; removing portions of the third conductive layer and the second insulating layer to form a control gate, a second gate insulating layer, a first opening and a second opening; forming a source region on the substrate; forming spacers; and forming a drain region on the substrate.