公开(公告)号：US07205603B2

公开(公告)日：2007-04-17

申请号：US10764037

申请日：2004-01-23

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

公开(公告)号：US07129537B2

公开(公告)日：2006-10-31

申请号：US11076499

申请日：2005-03-09

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract translation: 堆叠式栅极闪存器件及其制造方法。 层叠栅极闪存器件的单元被布置在衬底内的单元沟槽中，以实现存储单元的更高集成度。

公开(公告)号：US07005698B2

公开(公告)日：2006-02-28

申请号：US10668902

申请日：2003-09-23

Applicant: Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

Inventor： Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11553 ,  H01L29/42324 ,  H01L29/7885

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract translation: 分闸门闪存单元。 存储单元包括基板，导线，源极/漏极区，绝缘层，导电间隔物，绝缘柱，第一导电层和第一绝缘间隔物。 导线设置在衬底的沟槽的下部。 源极区域形成在与其上具有绝缘层的导电线的上部相邻的衬底中。 导电间隔物设置在用作浮动栅极的沟槽的上侧壁上。 绝缘支柱设置在绝缘层上。 第一导电层设置在与用作控制栅极的导电间隔物相邻的衬底上。 第一绝缘间隔件设置在绝缘螺柱的侧壁上以覆盖第一导电层。 漏极区域形成在与第一导电层相邻的衬底中。

公开(公告)号：US06872623B2

公开(公告)日：2005-03-29

申请号：US10395991

申请日：2003-03-24

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US06773993B2

公开(公告)日：2004-08-10

申请号：US09880783

申请日：2001-06-15

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L29/42332 ,  H01L21/28273

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

公开(公告)号：US06770532B2

公开(公告)日：2004-08-03

申请号：US10435447

申请日：2003-05-09

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6656

Abstract: A method for fabricating a memory unit with T-shaped gate. A semiconductor substrate forming a dielectric layer, a first opening, and a second opening is provided in a CMOS process. A silicate glass spacer is formed on the sidewall of the first opening and is thermally oxidized to form a light doped area under the silicate glass spacer. The silicate glass spacer is removed. An insulating spacer is formed on the sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. N-type conducting spacers are formed respectively on sidewalls of the insulating spacer and the first spacer. Gate dielectric layers are formed respectively in the first opening and the second opening. A P-type conducting layer fills with the first opening and the second opening, and a second spacer is formed on a sidewall of a conducting spacer of the second opening.

Abstract translation: 一种用于制造具有T形门的存储器单元的方法。 在CMOS工艺中提供形成电介质层，第一开口和第二开口的半导体衬底。 硅酸盐玻璃间隔物形成在第一开口的侧壁上，并被热氧化以在硅酸盐玻璃间隔物下面形成光掺杂区域。 去除硅酸盐玻璃间隔物。 绝缘垫片形成在第一开口的侧壁上。 第一间隔件形成在第二开口的侧壁上。 分别在绝缘间隔物和第一间隔物的侧壁上形成N型导电间隔物。 栅电介质层分别形成在第一开口和第二开口中。 P型导电层填充有第一开口和第二开口，并且第二间隔件形成在第二开口的导电间隔件的侧壁上。

公开(公告)号：US06713349B2

公开(公告)日：2004-03-30

申请号：US10426347

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for fabricating a split gate flash memory cell. First, a substrate having a doped region covered by a first conductive layer is provided. A floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer. Thereafter, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. The third insulating layer and the second conductive layer are successively etched back to expose the second insulating layer. The third insulating layer is removed using a cap layer formed on the second conductive layer as a mask to form an opening. Finally, the second conductive layer under the opening is removed to form a control gate underlying the cap layer.

Abstract translation: 一种用于制造分离栅闪存单元的方法。 首先，提供具有被第一导电层覆盖的掺杂区域的基板。 在第一导电层的两侧上的衬底上依次形成浮置栅极和第一绝缘层。 此后，在基板和第一绝缘层上依次形成适形的第二绝缘层和适形的第二导电层，然后在其上形成第三绝缘层。 连续蚀刻第三绝缘层和第二导电层以露出第二绝缘层。 使用形成在第二导电层上的盖层作为掩模去除第三绝缘层以形成开口。 最后，除去开口下方的第二导电层以形成位于盖层下面的控制栅。

公开(公告)号：US06649474B1

公开(公告)日：2003-11-18

申请号：US10426331

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66825

Abstract: A method for fabricating a source line of a flash memory cell. First, a substrate covered by a first insulating layer, a first conductive layer, and a second insulating layer successively is provided. Next, the second insulating layer is patterned to form an opening over the substrate and expose the first conductive layer. Next, a first spacer is formed over the sidewall of the lower opening and a second spacer is formed over the sidewall of the upper opening and the first spacer to make the opening has a “T” profile. Next, the exposed first conductive layer under the opening is removed, and a third spacer over the sidewall of the first spacer and the second spacer is formed. Finally, a source region is formed in the substrate under the opening and the opening is filled with a second conductive layer to form a source line.

Abstract translation: 一种用于制造闪存单元的源极线的方法。 首先，设置由第一绝缘层，第一导电层和第二绝缘层覆盖的基板。 接下来，对第二绝缘层进行图案化以在衬底上形成开口，并露出第一导电层。 接下来，在下开口的侧壁上形成第一间隔件，并且在上开口和第一间隔件的侧壁上形成第二间隔件，以使开口具有“T”轮廓。 接下来，去除开口下面露出的第一导电层，并且形成第一间隔物的侧壁上的第三间隔物和第二间隔物。 最后，在开口下方的基板中形成源极区域，并且开口填充有第二导电层以形成源极线。

公开(公告)号：US07476929B2

公开(公告)日：2009-01-13

申请号：US11269671

申请日：2005-11-09

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract translation: 本发明公开了一种具有间隔型浮动栅极的多位堆叠型非易失性存储器及其制造方法。 制造方法包括在半导体衬底上形成含有砷的图案化电介质层，其中图案化电介质层限定开口作为有效区域。 在图案化电介质层的侧壁上形成介质间隔物，并在半导体衬底上形成栅极电介质层。 源极/漏极区域通过使从扩散图案化的介电层扩散到半导体衬底中的热驱动方法形成。 间隔物形状的浮栅形成在电介质隔离物的侧壁和栅介电层上。 在间隔物形浮栅上形成层间绝缘层。 在层间电介质层上形成控制栅极，填充有源区的开口。

公开(公告)号：US20060063339A1

公开(公告)日：2006-03-23

申请号：US11269671

申请日：2005-11-09

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC: H01L21/331 ,  H01L21/8222

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract translation: 本发明公开了一种具有间隔型浮动栅极的多位堆叠型非易失性存储器及其制造方法。 制造方法包括在半导体衬底上形成含有砷的图案化电介质层，其中图案化电介质层限定开口作为有效区域。 在图案化电介质层的侧壁上形成介质间隔物，并在半导体衬底上形成栅极电介质层。 源极/漏极区域通过使从扩散图案化的介电层扩散到半导体衬底中的热驱动方法形成。 间隔物形状的浮栅形成在电介质隔离物的侧壁和栅介电层上。 在间隔物形浮栅上形成层间绝缘层。 在层间电介质层上形成控制栅极，填充有源区的开口。